Review of Xy Routing Algorithm for Network-on-Chip Architecture

Chawade, Shubhangi D; Gaikwad, Mahendra; Patrikar, Rajendra M.

doi:10.47893/ijcct.2016.1384

Cited by 13 publications

(11 citation statements)

References 13 publications

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“…The NoC MSwitch can be designed as 2D and 3D, in view of its directional information move. The XY steering [7][8][9] is followed in 2D, and XYZ direction is followed in 3D NoC. The 2D NoC MSwitch can process the information in five ways or through five information/yield ports.…”

Section: Literaturementioning

confidence: 99%

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

2021

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Network on chips (NoCs) 3D design expansion is continuously changing to produce energy-efficient NoCs. In this production, the major requirement is to have continuous monitoring with great effort of engineering process and policies which tries to incorporate the machine learning techniques for producing EE-NoCs (energy-efficient NoCs). The learning is a method of neural network system. This thought process of machine learning art in producing EE-NoCs resulted in better production. The internal architecture framed is Power Gate Deployment, voltage instant changeovers, and scaling in the frequenting simultaneous reduction in power. Multiprocessor architecture and platform have been introduced to extend the applicability of Moore's law. The solution for the multiprocessor system architecture is application-specific NoC architecture which are emerging as a leading technology. NoC can be useful in addressing many requirements such as inter-process communication, bandwidth, deadlock avoidance and routing structure. With power now the first order design constraint early stage estimation of NoC power, performance, and area has become important. The topology, switching and routing techniques are necessary in the NoC architecture design. This paper focuses on the n-dimension hypercube network on chip topological structure. It is used for more efficient performance and reliability for data communication. Therefore, in this paper, we are going to go through a bunch of different concepts, such as routing deadlock, and the router pipeline. Keywords Network on chip (NoC) • Power gate • Machine learning • Frequency scale • System on chip (SOC)This article is part of the topical collection "Computational Statistics" guest edited by Anish Gupta, Mike Hinchey, Vincenzo Puri, Zeev Zalevsky and Wan Abdul Rahim.

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Section: Literaturementioning

confidence: 99%

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

2021

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“…The NoC routing algorithm is the same as the routing algorithm of a computer network with area and cost constraints [5]. The routing algorithm is the set of rules used by the NoC router to traverse a packet from a source to a destination [7][8][9]. XY, West first, and random routing algorithms are oblivious congestion algorithms [10,11].…”

Section: Literature Reviewmentioning

confidence: 99%

Congestion‐Aware Routing Algorithm for NoC Using Data Packets

Ahmad

Sethi

Ullah

et al. 2021

Wireless Communications and Mobile Computing

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Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

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“…The most popular XY routing algorithm [19] is proposed by Wang Zhang and Ligang Hou in 2009. Based on literature [21], this study considered XY routing algorithm with 2×2 Mesh topology consisting of 4 nodes to validate data transfer as shown in Figure 2.…”

Section: 2xy Routing Algorithm For 2×2 Networkmentioning

confidence: 99%

An efficient FPGA based NoC architecture for data communication

Jamagoud¹,

Bhairannawar²

2018

IJACR

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NoC is a new model in which a single silicon chip is utilized to execute various communication features used in substantial to huge scale integration systems. NoC is another change to the universe of systems and also the other way to deal with disadvantages like wiring delay. There are numerous types of interconnections like point-to-point, bus architecture, carbon nanotubes, optical fiber [1] where NoC perform is better to reduce the interconnection issues in future designs. System on chips designed using NoCs are getting popular in these days which provide solutions to the problem related to bus based designs and considered as the future of the application specific integrated circuit (ASIC) design [2]. NoC basically has three building blocks router, links and network adapter (NA) [3]. NoC approach has numerous benefits over traditional bus method and also provides high throughput as buses are less scalable and limited bandwidth [4].

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Review of Xy Routing Algorithm for Network-on-Chip Architecture

Cited by 13 publications

References 13 publications

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

Congestion‐Aware Routing Algorithm for NoC Using Data Packets

An efficient FPGA based NoC architecture for data communication

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