Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures

Wei, Jiaxing; Wei, Zhaoxiang; Fu, Hao; Cao, Junhou; Wu, Tuanzhuang; Sun, Jie; Zhu, Xudong; Li, Sheng; Zhang, Long; Liu, Siyang; Sun, Weifeng

doi:10.1109/tpel.2023.3265864

Cited by 28 publications

(2 citation statements)

References 96 publications

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“…Silicon carbide (SiC) materials have higher bandwidth, critical breakdown field strength, electron saturation drift rate, and higher thermal conductivity than traditional Si materials. In turn, the corresponding SiC devices have higher voltage resistance, high temperature resistance, and higher frequency, with high efficiency and energy-saving advantages, which have great potential for future applications and are highly expected in the green energy revolution [ 1 , 2 , 3 , 4 , 5 , 6 ]. The horizontal hot wall design of the susceptor is now the dominant design in CVD applications for SiC growth, as it provides more uniform heat distribution and better precursor cracking efficiency.…”

Section: Introductionmentioning

confidence: 99%

Influence of Carbon Source on the Buffer Layer for 4H-SiC Homoepitaxial Growth

Yang,

Guo,

Zhao

et al. 2024

Materials

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In this study, we systematically explore the impact of C/Si ratio, pre-carbonization time, H2 etching time, and growth pressure on the buffer layer and subsequent epitaxial layer of 6-inch 4H-SiC wafers. Our findings indicate that the buffer layer’s C/Si ratio and growth pressure significantly influence the overall quality of the epitaxial wafer. Specifically, an optimal C/Si ratio of 0.5 and a growth pressure of 70 Torr yield higher-quality epitaxial layers. Additionally, the pre-carbonization time and H2 etching time primarily affect the uniformity and surface quality of the epitaxial wafer, with a pre-carbonization time of 3 s and an H2 etching time of 3 min found to enhance the surface quality of the epitaxial layer.

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Section: Introductionmentioning

confidence: 99%

Influence of Carbon Source on the Buffer Layer for 4H-SiC Homoepitaxial Growth

Yang,

Guo,

Zhao

et al. 2024

Materials

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“…As to a repetitive UIS failure mechanism, it is commonly believed that a hot hole in the JFET region will be injected into oxide and trapped by the interface states and gate oxide leading to the parameters’ degradation. However, there are fewer comprehensive studies [ 7 , 20 , 21 ] on UIS failure mechanisms including temperature characteristics and some important circuit loop parameters under single and repetitive UIS stress on trench gate MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4H-SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor Structures

Liu,

Guo,

Shi

et al. 2024

Micromachines

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This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical–thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters’ degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability.

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