“…To verify the proposed architecture, we have implemented the proposed crypto algorithm using VHDL (LaMeres, 2017) to describe the compressor on the Altera Cyclone IV FPGA chip family (Altera Corporation, 2012a). The completed design of SSC composes several design modules including the random number generation (Tian et al, 2009;Abu Al-Haija et al, 2018b), primality testing (Ishmukhametov and Mubarakov, 2013;Asad et al, 2017a), arithmetic addition units (Ercegovac and Lang, 2004;Marouf et al, 2017a), arithmetic multiplication unit (Karatsuba and Ofman, 1963;Asad et al, 2017b;Asad et al, 2019), greatest common divisor (GCD), and least common multiple (LCM) units (Brent and Kung, 1984;Stein, 2009;Marouf et al, 2017b), modular exponentiation unit (Walter, 2010;Marouf et al, 2017c), and modular inverse unit (Hlaváč and Lórencz, 2013;Al-Haija et al, 2018). Finally, we have synthesized the resulting hardware coding using Quartus II CAD design tool (Altera Corporation, 2012b), which confirms that SSC can be used as an efficient and comparable alternative to RSA for securing the wireless sensor networks (Abu Al-Haija et al, 2014).…”