Revision and verification of an enhanced UART

Gallo, Roberto; Delvai, Martin; Elmenreich, Wilfried; Steininger, Andreas

doi:10.1109/wfcs.2004.1377735

Cited by 11 publications

(4 citation statements)

References 1 publication

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“…To avoid aliasing, improve resolution, and reduce noise, an oversampling scheme is used to extracts the bit value of the signal received. A rate of 16 times the baud rate is the most widely used for oversampling frequency in the design of the UARTs [21][22][23].…”

Section: Uart a Wireless Communication Module Is Connectedmentioning

confidence: 99%

FPGA Based Single Chip Solution with 1-Wire Protocol for the Design of Smart Sensor Nodes

2014

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Applications that involve monitoring of water quality parameters require measuring devices to be placed at different geographical locations but are controlled centrally at a remote site. The measuring devices in such applications need to be small, consume low power, and must be capable of local processing tasks facilitating the mobility to span the measuring area in a vast geographic area. This paper presents the design of a generalized, low-cost, reconfigurable, reprogrammable smart sensor node using a ZigBee with a Field-Programmable Gate Array (FPGA) that embeds all processing and communication functionalities based on the IEEE 1451 family of standards. Design of the sensor nodes includes processing and transducer control functionalities in a single core increasing the speedup of processing power due to interprocess communication taking place within the chip itself. Results obtained by measuring the pH value and temperature of water samples verify the performance of the proposed sensor node.

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Section: Uart a Wireless Communication Module Is Connectedmentioning

confidence: 99%

FPGA Based Single Chip Solution with 1-Wire Protocol for the Design of Smart Sensor Nodes

2014

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“…If the frequency of the clock signal is inaccurate, it can cause an error between the actual baud rate and the expected baud rate. Clock errors can be caused by factors such as crystal oscillators, temperature, voltage changes, and more [8].…”

Section: Baud Rate Deviation Adjustmentmentioning

confidence: 99%

Analysis of the baud rate of the UART to affects the data

Huang¹,

Hua²,

Zhang³

2023

HSET

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This article explores the impact of different baud rates on Universal Asynchronous Receiver/Transmitter (UART) asynchronous serial communication. It discusses the frame format and calculation method of baud rate error, as well as the main reasons for error, such as clock error, sampling error, line noise, data bit error, and software delay. To ensure reliable communication, it is essential to test and debug the actual baud rate and adjust it accordingly. The study found that higher expected baud rates resulted in higher baud rate errors, affecting transmission distance, speed, reliability, and system complexity. The appropriate baud rate should be selected based on specific application scenarios and requirements. Higher baud rates are needed for high-speed transmissions, while lower baud rates are required for long transmission distances or high reliability requirements. However, further research is needed to determine the impact of unallocated baud rates on data. Overall, this article provides valuable insights into the development of UART.

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“…In the error correction mode, (8,4) extended hamming code, also called as SEC-DED code, is employed for single bit error correction and double error detection. In this mode four data bits are transmitted per frame.…”

Section: Proposed Architecture Of Uartmentioning

confidence: 99%

A novel VHDL implementation of UART with single error correction and double error detection capability

Muppalla¹,

Rao²

2015

2015 International Conference on Signal Processing and Communication Engineering Systems

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In an industrial working environment employing multiprocessor communication using UART, noise is likely to affect the data and data may be received with errors. This kind of error occurrence may affect the working of the system resulting in an improper control. Several existing UART designs are incorporating error detection logic. This kind of logic, if detects errors, requires retransmission of corresponding data frames which take additional time for automatic repeat request (ARQ) and retransmission of data. Linear block codes like hamming code have forward error correction (FEC) as well as error detection capability. This paper presents a novel VLSI implementation of UART designed to include (8,4) extended hamming code called SEC-DED code that can correct upto one error and detect upto two errors. This improves the noise immunity of the system optimizing the error free reception of data. The whole design is implemented in Xilinx ISE 12.3 simulator targeted to Xilinx Spartan 6 FPGA.

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Revision and verification of an enhanced UART

Cited by 11 publications

References 1 publication

FPGA Based Single Chip Solution with 1-Wire Protocol for the Design of Smart Sensor Nodes

FPGA Based Single Chip Solution with 1-Wire Protocol for the Design of Smart Sensor Nodes

Analysis of the baud rate of the UART to affects the data

A novel VHDL implementation of UART with single error correction and double error detection capability

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