Revisiting Persistent Indexing Structures on Intel Optane DC Persistent Memory

Bu, Heng; Dong, Mingkai; Yi, Jifei; Zang, Binyu; Chen, Haibo

doi:10.1007/s11390-020-9871-0

Cited by 5 publications

(5 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…While the recently-launched Intel Ice Lake processors with Optane persistent memory 200 series may provide flush instructions that do not invalidate the flushed cache lines, existing NVRAM architectures with Cascade Lake processors do not seem to support such instructions. Our impression is corroborated in the findings of [5,15,17,20,28,49,51]. Existing (costly) architectures will probably remain in use for years to come and one needs to use algorithmic modifications to obtain improved performance on such machines.…”

Section: Introductionsupporting

confidence: 56%

“…This is also noted by others [e.g. 5,15,17,20,28,49,51]. The recently-launched Third Generation Intel Xeon Scalable Ice Lake processors with Optane persistent memory 200 series may implement CLWB retaining lines in the cache, but NVRAM platforms currently in the market do not seem to support flushes without cache invalidation.…”

Section: Modelmentioning

confidence: 70%

“…The recovery procedure resurrects all nodes reachable from the head through a path of consecutive nodes with the initialized flag set. It remains to ensure that completed enqueue operations are visible to the recovery procedure, even though previous nodes 5 in the queue may have been enqueued by operations that have not yet completed. Before an enqueue operation completes, LinkedQ makes sure that all data on nodes from the head to the enqueued node is written back to the NVRAM.…”

Section: Linkedqmentioning

confidence: 99%

See 2 more Smart Citations

Durable Queues: The Second Amendment

Sela,

Petrank

2021

Preprint

View full text Add to dashboard Cite

We consider durable data structures for non-volatile main memory, such as the new Intel Optane memory architecture. Substantial recent work has concentrated on making concurrent data structures durable with low overhead, by adding a minimal number of blocking persist operations (i.e., flushes and fences). In this work we show that focusing on minimizing the number of persist instructions is important, but not enough. We show that access to flushed content is of high cost due to cache invalidation in current architectures. Given this finding, we present a design of the queue data structure that properly takes care of minimizing blocking persist operations as well as minimizing access to flushed content. The proposed design outperforms state-of-the-art durable queues.We start by providing a durable version of the Michael Scott queue (MSQ). We amend MSQ by adding a minimal number of persist instructions, fewer than in available durable queues, and meeting the theoretical lower bound on the number of blocking persist operations. We then proceed with a second amendment to this design, that eliminates accesses to flushed data. Evaluation shows that the second amendment yields substantial performance improvement, outperforming the state of the art and demonstrating the importance of reduced accesses to flushed content. The presented queues are durably linearizable and lock-free. Finally, we discuss the theoretical optimal number of accesses to flushed content. CCS CONCEPTS• Theory of computation → Data structures design and analysis; • Computing methodologies → Shared memory algorithms; Concurrent algorithms; • Hardware → Emerging architectures; Non-volatile memory.

show abstract

Section: Introductionsupporting

confidence: 56%

Section: Modelmentioning

confidence: 70%

Section: Linkedqmentioning

confidence: 99%

See 1 more Smart Citation

Durable Queues: The Second Amendment

Sela,

Petrank

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…So far, there is one industrial NVM module supplied by Intel in 2019, which is called the Intel Optane DC Persistent Memory [10]. However, in this paper, we still use a simulation way to simulate the hybrid memory using DRAM.…”

Section: A Settingsmentioning

confidence: 99%

NVMSorting: Efficient Sorting on Non-Volatile Memory

Chu¹

2021

Proceedings of the 33rd International Conference on Software Engineering and Knowledge Engineering

View full text Add to dashboard Cite

Non-volatile memory (NVM) as a new type of storage technology has many advantages such as non-volatility, byte addressability, high storage-density, and low energy consumption. Meanwhile, NVM has some limitations, e.g., asymmetric read and write latency, limited write endurance, and high price. Therefore, at present, it is not realistic to completely replace DRAM with NVM in computer systems. A more feasible scheme is to adopt the hybrid memory architecture composed of NVM and DRAM. Following the assumption of hybrid memory architecture, this paper proposes an NVM-friendly sorting algorithm called NVMSorting. Particularly, we introduce a new concept called natural runs to improve the existing MONTRES algorithm and present the cost analysis of the algorithm in the hybrid memory architecture. In order to verify the performance of our proposal, we implement six existing sorting algorithms as baselines, including the MONTRES algorithm, and conduct comparative experiments on an unsorted dataset and a partially sorted dataset. The experimental results suggest the efficiency of NVMsorting in terms of execution time and NVM writes. Especially, on the partially sorted dataset, NVMSorting has 6.2% improvement on time performance and 5.7% reduction on NVM writes compared to MONTRES, and 13.0% performance improvement and 27.1% NVM-write reduction compared to the traditional merge sorting algorithm.

show abstract

“…The ML technique is mainly used here to improve the accuracy of prediction and evaluation processes. Indexing systems require accurate data provided by the evaluation process (Bu et al, 2021). The deep reinforcement learning (DRL) algorithm is mainly used for evaluation.…”

Section: Introductionmentioning

confidence: 99%

Research on an evaluation index system of critical emergency management capability based on machine learning in a complex scientific environment

Zhao

2023

Front. Ecol. Evol.

View full text Add to dashboard Cite

IntroductionA complex scientific environment requires multiple considerations for handling critical and emergency conditions with an addressing solution. Indexing and prioritizing are standard methods that are used in such settings to improve itinerary solutions. Significance of an indexing system relies on the benchmark solution and the strategy it implies.MethodsThe present study introduces an indexing strategy evaluation method (ISEM) to validate the efficiency of indexing systems. The proposed method identifies the root implication and the strategy parameters to address complex problems. The environmental and problem-specific parameters are determined to estimate the system's initial response. The capability through solution response, lag, and failure analysis is identified post the estimation through linear regression learning. The indexing system's operations are designed through linear itineraries to prevent interrupting failures. In addition, the environmental features are identified as augmenting factors to prevent strategy pausing across multiple indices.Results and discussionThe proposed method employs linear analysis through itinerary levels of index evaluation for optimal, lagging, and failed implications. It also helps to identify specific reasons for solution improvement or retention from previous operations.

show abstract

Revisiting Persistent Indexing Structures on Intel Optane DC Persistent Memory

Cited by 5 publications

References 36 publications

Durable Queues: The Second Amendment

Durable Queues: The Second Amendment

NVMSorting: Efficient Sorting on Non-Volatile Memory

Research on an evaluation index system of critical emergency management capability based on machine learning in a complex scientific environment

Contact Info

Product

Resources

About