Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

Abstract

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

RETRACTED: An improved hybrid network‐on‐chip with flexible topology and frugal routing

“…The wired part of the network is a mesh spread out. In an early investigation [25], 2D mesh and 3D torus exhibited good throughput with the varying network size, number of nodes sending messages, and message size. Considering the problems associated with 3D technology, such as vertical via failure and heat dissipation, the 2D mesh was chosen for the wired network.…”

“…The waveguide provides a communication channel that is well-known during the design phase. Most importantly, the design and size of RF elements for such NoC architectures have been widely discussed in the literature [16][17][18][19], proving the approach's viability.…”

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

“…However, the difficulty behind such a low-level design is the long time associated with FPGA development cycles. Overlay architectures have been introduced by such initiatives as ZUMA [37], Quku [38] and DeCO [39] with the aim to increase the abstraction level, improve the productivity, ease the programmability and reduce the time of design [40].…”

Multi-Cloud: A Comprehensive Review

“…The paper empirical evaluated the performance loss that occurs because of the use of interpreted languages for HPC. [30] is a comprehensive survey of three main aspects: non-standard terms in existing literature, network-on-chip evaluation decisions as a means for exploring communication architecture, and latest classification virtualization methods. Table 1 given below summarizes the techniques being discussed across the literature.…”