RF/Analog performance of GaAs Multi-Fin FinFET with stress effect

Das, Rinku Rani; Maity, Santanu; Chowdhury, Arijit; Chakraborty, Apurba

doi:10.1016/j.mejo.2021.105267

Cited by 12 publications

(6 citation statements)

References 27 publications

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“…( 9) and Eq. ( 10), the maximum conversion efficiency of the proposed cell can be rewritten as: η = FFV oc J sc P in (11) where, P in = I (λ) dλ is the incident optical power and F is the cell filling factor, which is represented by (12) as:…”

Section: Resultsmentioning

confidence: 99%

“…Effective light-trapping structures have various design considerations studying the effect of these structures on the cell efficiency versus the active layer thickness [1]- [10]. Other techniques implement perovskite solar cells using organic/inorganic active layer for efficiency enhancement and studying the radio frequency performance of GaAs material [11]- [14]. Reducing light reflection on the surface of solar cells is a key factor in increasing the amount of light absorption, and hence, the conversion efficiency.…”

mentioning

confidence: 99%

“…The important result in these research papers is the contribution of the light-trapping structures to the active layer thickness and efficiency. In [11]- [14], authors proved new organic, inorganic, and hybrid inorganic-organic inverted cells with a barrier layer and active organic active layer for efficiency and reliability enhancement. Also, the authors demonstrate a carrier collection mechanism using a hole-collection treated graphene layer.…”

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confidence: 99%

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Efficiency Enhancement of GaAs Nano Solar Cell Based on 2D Photonic Crystal Trapping Layer and 2D Index Modulation Layer

Morsy

Saleh

2022

IEEE Access

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In this paper, a nano solar cell structure based on a two-dimensional photonic crystal (2D-PhC) antireflection coating (ARC) trapping layer and a 2D-graded-index (2D-GI) GaAs active layer is presented. These components improve the solar absorption, in-coupling efficiency, quantum efficiency, and optical properties of the active layer. The proposed cell absorption and conversion efficiency were analyzed as a function of the cell layer thickness in comparison with the Lambertian absorption and cell efficiency limits. Additionally, each layer thickness was optimized to enhance the overall solar efficiency. All simulations were conducted in the 300 to 1100 nm range using finite difference time domain (FDTD) analysis, where the 2D-PhC structure was represented by indium tin oxide (ITO) nanorods in an air background. In addition, p-Al(0.85)GaAs/n-Al(0.35)GaAs two-window confinement layers are utilized in contact with the 907-nm GaAs active layer as a perfect match with the 1840-nm ITO-ARC layer to improve the confinement efficiency. Moreover, p-Al(0.85)GaAs/GaAs and GaAs/n-Al(0.35)GaAs 2D-GI active layer structures are used for index modulation to enhance the active layer properties and increase the cell short-circuit current. The main objective of this study is to determine the optimum design of a solar cell that can provide the highest power conversion efficiency using inexpensive semiconductor materials. One of the expected results from this research is the design of a 100-µm 2 nano solar cell with 39.2% conversion efficiency, a short circuit current density of 44.38 mA/cm 2 , and an open-circuit voltage of 1 V. INDEX TERMSTwo-dimensional photonic crystal (2D-PhC), light trapping, 2D-index modulation, absorption, conversion efficiency, short circuit current, open circuit voltage.

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Efficiency Enhancement of GaAs Nano Solar Cell Based on 2D Photonic Crystal Trapping Layer and 2D Index Modulation Layer

Morsy

Saleh

2022

IEEE Access

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“…In principle, the ultrascaled FinFETs tend to adopt uniform multifin arrays to achieve high-density integration and robust performance in terms of power gain and drive capability for logic chips [34][35][36][37] . As compared to single-fin FETs, multi-fin FETs might offer a larger total channel width, resulting in higher total drive current, transconductance, and lower noise 35 .…”

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confidence: 99%

Integrated 2D multi-fin field-effect transistors

Yu,

Tan,

Yin

et al. 2024

Nat Commun

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Vertical semiconducting fins integrated with high-κ oxide dielectrics have been at the centre of the key device architecture that has promoted advanced transistor scaling during the last decades. Single-fin channels based on two-dimensional (2D) semiconductors are expected to offer unique advantages in achieving sub-1 nm fin-width and atomically flat interfaces, resulting in superior performance and potentially high-density integration. However, multi-fin structures integrated with high-κ dielectrics are commonly required to achieve higher electrical performance and integration density. Here we report a ledge-guided epitaxy strategy for growing high-density, mono-oriented 2D Bi2O2Se fin arrays that can be used to fabricate integrated 2D multi-fin field-effect transistors. Aligned substrate steps enabled precise control of both nucleation sites and orientation of 2D fin arrays. Multi-channel 2D fin field-effect transistors based on epitaxially integrated 2D Bi2O2Se/Bi2SeO5 fin-oxide heterostructures were fabricated, exhibiting an on/off current ratio greater than 106, high on-state current, low off-state current, and high durability. 2D multi-fin channel arrays integrated with high-κ oxide dielectrics offer a strategy to improve the device performance and integration density in ultrascaled 2D electronics.

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“…However, when dimensions decrease below the 5-nm node, FinFETs encounter several issues. The electric field at the sidewall is always enhanced compared to the corner's electric field, decreased device performance, decreased electrostatics, and significant process variability [4] - [8].…”

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confidence: 99%

Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes

Gowthami,

Kumar Panigrahy,

Shobha Rani

et al. 2024

IEEE Access

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Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (LG) n-type Tree-shaped NSFET with the gate having a stack of high-k dielectric (HfO2) and SiO2 using different spacer materials, which can be done using TCAD simulations. The Tree-shaped NFET device with T(NS) = 5 nm, W(NS) = 25 nm, WIB = 5 nm, and HIB = 25 nm has high on-current (ION) and low off-current (IOFF). The 3D device with single-k and dual-k spacers are compared and its DC characteristics are shown. It is noted that the dual-k device achieves the maximum ION/IOFF ratio, which is 10 9 , compared to 10 7 because the fringing fields with spacer dielectric lengthen the effective gate length. Additionally, the impact of work function, interbridge height, width, gate lengths, and temperature, along with the device's analog/RF and DC metrics, is also investigated in this paper. Even at 12 nm LG, the proposed device exhibits good electrical properties with DIBL = 23 mV/V and SS = 62 mV/dec and switching ratio (ION/IOFF) = 10 9 . The device's performance confirms that Moore's law holds even for lower technology nodes, allowing for further scalability.

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RF/Analog performance of GaAs Multi-Fin FinFET with stress effect

Cited by 12 publications

References 27 publications

Efficiency Enhancement of GaAs Nano Solar Cell Based on 2D Photonic Crystal Trapping Layer and 2D Index Modulation Layer

Efficiency Enhancement of GaAs Nano Solar Cell Based on 2D Photonic Crystal Trapping Layer and 2D Index Modulation Layer

Integrated 2D multi-fin field-effect transistors

Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes

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