RF characterization and small signal extraction on 22 nm CMOS fully-depleted SOI technology

Kane, Ousmane Magatte; Lucci, L.; Scheiblin, P.; Lepilliet, S.; Danneville, F.

doi:10.1109/eurosoi-ulis45800.2019.9041863

Cited by 6 publications

(2 citation statements)

References 6 publications

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“…As high fT is usually ass with lower device NF, we have biased several N-MOSFET to reach fT above ~340 G study their noise performance, as shown in Table 1. However, unlike the device's N is known to be less sensitive to the transistor's layout parasitics resistance and capac Similar to NFmin, fMAX is highly dependent on the layout of the transistor, and sinc 22FDX offers options to vary the contact poly pitch (CPP, see Figure 2), the effects on NFmin and fMAX were explored in pre-PEX simulation [14]. As shown in Table 1, t tors with pitches that are 208 nm (CPP2x) have higher fMAX than the narrower pitched (CPP1x) devices, and their differences become more significant as the total widt creased.…”

Section: Contact Poly Pitch (Cpp)mentioning

confidence: 99%

“…Similarly, NF min at 28 GHz is consistently better for the CPP2x devices as they are lower than the CPP1x devices. This is because a wide pitch in CPP2x devices can fit more drain and source contacts, and due to the increased contact areas, the drain and source resistance is effectively reduced and, therefore, both NF min and f MAX are improved [14]. Consequently, a CPP of 208 nm is selected for all NMOS devices used in this design.…”

Section: Contact Poly Pitch (Cpp)mentioning

confidence: 99%

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A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

Ouyang,

Mayeda,

Sweeney

et al. 2024

Applied Sciences

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This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

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Section: Contact Poly Pitch (Cpp)mentioning

confidence: 99%

Section: Contact Poly Pitch (Cpp)mentioning

confidence: 99%

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

Ouyang,

Mayeda,

Sweeney

et al. 2024

Applied Sciences

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Small-Signal Characterization and Modelling of a Back Bias Reconfigurable Field Effect Transistor

Wesling,

Deng,

Chohan

et al. 2024

2024 IEEE European Solid-State Electronics Research Conference (ESSERC)

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In this work, we present the first small signal characterization of a reconfigurable field effect transistor. The device under test is a back-bias RFET integrated into an industrial 22nm FDSOI platform. These devices are particularly interesting for CMOS co-design as they enable a frequency doubling functionality using a single transistor, without the need for inductive elements. Extraction of figures of merit and a comprehensive small signal analysis are performed. It is demonstrated that an ambipolar back-bias reconfigurable field-effect transistor can be modelled using a conventional small-signal equivalent circuit. This shows promise for modelling engineers and circuit designers to explore innovative applications of this new emerging technology.

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Characterization of 22 nm FDSOI nMOSFETs With Different Backplane Doping at Cryogenic Temperature

Xie

Wang

et al. 2021

IEEE J. Electron Devices Soc.

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In this work, the electrostatic and radio frequency performances of 22 nm FDSOI nMOSFETs with p-type or n-type doped backplane (BP, highly doped layer of silicon below thin buried oxide) at cryogenic temperatures have been investigated. Greater enhancement of drain current I d , maximum transconductance g m,max and threshold voltage V TH values have been demonstrated at liquid nitrogen temperatures. Furthermore, FDSOI nMOSFETs with n-type BP achieve the maximum transconductance at lower bias voltage and smaller V ZTC , which is mainly due to its small threshold voltage. The variation of threshold voltage of BP-p devices is greater with the decrease of temperature. About 40% improvement of f T and 30% improvement of f max depended on the W f of devices have been shown. Relevant small-signal parameters (e.g., transconductance g m , gate capacitance C gg , gate resistance R g and output conductance g ds ) are also extracted for comparison and analysis. This study presents both 22 nm FDSOI nMOSFETs with p-type or n-type backplane as good candidates for cryogenic applications down to 77 K, and especially, BP-n FDSOI are more suitable for low power operation applications because of their lower threshold voltage. Similar g m.max and the peak values of RF FOMs can be obtained at lower bias voltage compared with BP-p devices.INDEX TERMS Backplane (BP) doping, cryogenic, fully-depleted silicon-on-insulator (FDSOI), RF

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RF characterization and small signal extraction on 22 nm CMOS fully-depleted SOI technology

Cited by 6 publications

References 6 publications

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

Small-Signal Characterization and Modelling of a Back Bias Reconfigurable Field Effect Transistor

Characterization of 22 nm FDSOI nMOSFETs With Different Backplane Doping at Cryogenic Temperature

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