RF Clock Distribution System for a Scalable Quantum Processor in 22-nm FDSOI Operating at 3.8 K Cryogenic Temperature

Bashir, Imran; Leipold, Dirk; Asker, Mike; Esmailiyan, Ali; Wang, Hongying; Siriburanon, Teerachot; Giounanlis, Panagiotis; Kozioł, Anna; Miceli, Dennis A.; Blokhina, Elena; Staszewski, Robert Bogdan

doi:10.1109/rfic49505.2020.9218321

Cited by 5 publications

(4 citation statements)

References 5 publications

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“…[31][32][33] . tuning elements 30 . The clock signal path should be low loss over a wide bandwidth, which enhances the operating range and resolution of the pulse generator.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…The calculations include active and passive loads from cabling connected to DUT including the RF coax carrying the chip clock. Some parameters in the table are taken from 30,34 . .…”

Section: Heat Load Calculationsmentioning

confidence: 99%

“…For active load, the square of the average supply current is multiplied by the calculated wire resistance. The heat dissipation from the RF signal is due to the cable loss of 2 dB 30 and the 50 Ω termination at the 3K stage. The total thermal load is 21 mW which is 1.5% of the 1.5 W specification.…”

Section: Heat Load Calculationsmentioning

confidence: 99%

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Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process

Bashir¹,

Leipold²,

Elena³

et al. 2021

Preprint

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The proliferation of quantum computing technologies has fueled the race to build a practical quantum computer. The spectrum of the innovation is wide and encompasses many aspects of this technology, such as the qubit, control and detection mechanism, cryogenic electronics, and system integration. A few of those emerging technologies are poised for successful monolithic integration of cryogenic electronics with the quantum structure where the qubits reside. In this work, we present a fully integrated Quantum Processor Unit in which the quantum core is co-located with control and detection circuits on the same die in a commercial 22-nm FD-SOI process from GlobalFoundries. The system described in this work comprises a two dimensional (2D) 240 qubits array integrated with 8 detectors and 32 injectors operating at 3 K and inside a two-stage Gifford -McMahon cryo-cooler. The power consumption of each detector and injector is 1 mW and 0.27 mW, respectively. The control sequence is programmed into an on-chip pattern generator that acts as a command and control block for all hardware in the Quantum Processor Unit. Using the aforementioned apparatus, we performed a quantum resonant tunneling experiment on two qubits inside the 2D qubit array. With supporting lab measurements, we demonstrate the feasibility of the proposed architecture in scaling-up the existing quantum core to thousands of qubits.

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“…[31][32][33] . tuning elements 30 . The clock signal path should be low loss over a wide bandwidth, which enhances the operating range and resolution of the pulse generator.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…The calculations include active and passive loads from cabling connected to DUT including the RF coax carrying the chip clock. Some parameters in the table are taken from 30,34 . .…”

Section: Heat Load Calculationsmentioning

confidence: 99%

See 1 more Smart Citation

Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process

Bashir¹,

Leipold²,

Elena³

et al. 2021

Preprint

Self Cite

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“…(d) Cross-section transmission electron microscopy (TEM) photo of the proposed QD array (QDA) in 22FDX together with the end-of-row injection and extraction interface device or single-electron injection devices [131]. (e) Top-view TEM photo of the QDA in 22FDX with upper (annotated) and lower rows coupled electrostatically through an interaction gate at the middle, and connected to classical electronics through interface devices [131], (f) TEM picture of 1/2 of QDA with schematic of interfacing circuitry [132], (g) die microphotograph of a quantum experiment cell part of the quantum SoC in 22FDX (left), and the printed circuit board (PCB) with the quantum SoC at the center (right) [192].…”

Section: ) Research At Equal1mentioning

confidence: 99%

CMOS Integrated Circuits for the Quantum Information Sciences

Anders

Babaie

Bardin

et al. 2023

IEEE Trans. Quantum Eng.

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Over the past decade, significant progress in quantum technologies has been made and, hence, engineering of these systems has become an important research area. Many researchers have become interested in studying ways in which classical integrated circuits can be used to complement quantum mechanical systems, enabling more compact, performant, and/or extensible systems than would be otherwise feasible. In this article-written by a consortium of early contributors to the field-we provide a review of some of the early integrated circuits for the quantum information sciences. CMOS and BiCMOS integrated circuits for nuclear magnetic resonance, nitrogen-vacancy-based magnetometry, trapped-ion-based quantum computing, superconductor-based quantum computing, and quantum-dot based quantum computing are described. In each case, the basic technological requirements are presented before describing proof-of-concept integrated circuits. We conclude by summarizing some of the many open research areas in the quantum information sciences for CMOS designers.

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Monolithically Integrated Quantum Dots in a 22‐nm Fully Depleted Silicon‐on‐Insulator Process Operating at 3 K

Bashir,

Sokolov,

et al. 2024

Circuit Theory & Apps

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Quantum computers comprising large‐scale arrays of qubits will enable complex algorithms to be executed to provide a quantum advantage for practical applications. A prerequisite for this milestone is a power‐efficient qubit control and detection system operating at cryogenic temperatures. Implementing such systems in complementary metal‐oxide‐semiconductor (CMOS) technology offers clear advantages in terms of scalability. Here, we present a fully integrated quantum dot array in which silicon quantum wells are co‐located with control and detection circuitry on the same die in a commercial 22‐nm fully depleted silicon‐on‐insulator (FDSOI) process. Our system comprises a two‐dimensional quantum dot array, integrated with 8 detectors and 32 injectors, operating at 3 K inside a cryo‐cooler. The power consumption of the control and detection circuitry is 2.5 mW per qubit without body biasing. The design utilizes 0.8‐V nominal devices. The setup allows us to verify discrete charge injection control and detection at the quantum dot array and demonstrate the feasibility of this architecture for scaling up the existing quantum core to hundreds and thousands of physical qubits.

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RF Clock Distribution System for a Scalable Quantum Processor in 22-nm FDSOI Operating at 3.8 K Cryogenic Temperature

Cited by 5 publications

References 5 publications

Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process

Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process

CMOS Integrated Circuits for the Quantum Information Sciences

Monolithically Integrated Quantum Dots in a 22‐nm Fully Depleted Silicon‐on‐Insulator Process Operating at 3 K

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