RF Performance Improvement of InP Frequency Divider by Using Enhanced f
 
 T
 -Doubler Technique

Zhen, Wenxiang; Xiao, Luning; Cao, Shurui; Su, Yongbo; Jin, Zhi

doi:10.1109/lmwc.2022.3169807

Cited by 3 publications

(2 citation statements)

References 20 publications

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“…So far, numerous dividers based on different topologies and processes have been reported. Silicon-Germanium (SiGe) [11,12,13] and indium phosphide (InP) [14,15,16,17,18,19] are employed in many high-speed ECL dividers due to their high unity-gain (cut-off) frequency ( 𝑓 𝑡 ).In addition, several methods documented in the literature extend the operating frequency range of frequency dividers. These techniques include inductive peaking [20], split resistors [3], negative capacitance technology [21], and capacitive degeneration [22].In 1972, a differential implementation of the 𝑓 𝑡 -doubler structure was patented for the first time by Carl R. Batties [23], then it was applied in many field [24,25,26,27,28].…”

Section: Introductionmentioning

confidence: 99%

A broadband ECL static frequency divider in InP DHBT using differential ft-doubler

Xu,

Lou,

et al. 2024

IEICE Electron. Express

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This letter presents a broadband ECL static divider using a 0.8-μ m InP DHBT process. The differential implementation of 𝑓 𝑡 doubler has been employed to extend the bandwidth at the cost of little increase in power dissipation and chip area. The frequency characteristics of the 𝑓 𝑡 -doubler circuit were analyzed. The chip area was 0.47mm*0.44mm and the total power dissipation was 417 mW from dual power supplies of -3.5 V and -2.5 V. The measurement result shows that the frequency divider can operate from 2 GHz to 66 GHz for sinusoidal input signal. The input reference SOF (self-oscillation frequency) is 59 GHz. the output power locates in 0.41 -10.35 dBm. This divider can operate within a frequency range of 2 GHz to 66 GHz, exhibiting a 0.4-𝑓 𝑡 frequency range.

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Section: Introductionmentioning

confidence: 99%

A broadband ECL static frequency divider in InP DHBT using differential ft-doubler

Xu,

Lou,

et al. 2024

IEICE Electron. Express

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“…For instance, work [11] put forward a THA with an inductive peaking input stage to improve the bandwidth, which was applied in a time-interleaved flash ADC. In our previous work [7], an enhanced cut-off frequency doubler ( f T -doubler) method was proposed based on the traditional f T -doubler technique [18,19,20] to boost the bandwidth. Except for the classic techniques above, the Darlington f T -doubler structures can also be used for high-speed applications, where patent [21] IEICE Electronics Express, Vol.VV, No.NN, 1-6 put forward and briefly elaborated its basic theory.…”

Section: Introductionmentioning

confidence: 99%

Enhanced Darlington fT-doubler Structure in a 25 GS/s Track-and-Hold Amplifier for Bandwidth Improvement

Xiao

Zhen

et al. 2023

IEICE Electron. Express

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A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8µm indium phosphide (InP) process with 165 GHz cut-off frequency ( f T ). Broadband operation is achieved using an enhanced degenerated Darlington f T -doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f T -doubler structures, the enhanced cascode Darlington f T -doubler structure reduces the "V C E mismatch" between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V C E for amplifying transistors, which represents higher f T , p e ak performance. Benefiting from the proposed Darlington f T -doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181f T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

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Accurate Modeling Approach for InP f _T-Doubler Based on Electromagnetic Simulation

Wang

Ding

Feng

et al. 2023

IEEE Trans. Electron Devices

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RF Performance Improvement of InP Frequency Divider by Using Enhanced f _T-Doubler Technique

Cited by 3 publications

References 20 publications

A broadband ECL static frequency divider in InP DHBT using differential <i>f<sub>t</sub></i>-doubler

A broadband ECL static frequency divider in InP DHBT using differential <i>f<sub>t</sub></i>-doubler

Enhanced Darlington <i>f<sub>T</sub></i>-doubler Structure in a 25 GS/s Track-and-Hold Amplifier for Bandwidth Improvement

Accurate Modeling Approach for InP f _T-Doubler Based on Electromagnetic Simulation

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RF Performance Improvement of InP Frequency Divider by Using Enhanced f T -Doubler Technique

Cited by 3 publications

References 20 publications

A broadband ECL static frequency divider in InP DHBT using differential <i>f<sub>t</sub></i>-doubler

A broadband ECL static frequency divider in InP DHBT using differential <i>f<sub>t</sub></i>-doubler

Enhanced Darlington <i>f<sub>T</sub></i>-doubler Structure in a 25 GS/s Track-and-Hold Amplifier for Bandwidth Improvement

Accurate Modeling Approach for InP f T-Doubler Based on Electromagnetic Simulation

Contact Info

Product

Resources

About

RF Performance Improvement of InP Frequency Divider by Using Enhanced f _T-Doubler Technique

Accurate Modeling Approach for InP f _T-Doubler Based on Electromagnetic Simulation