RFCMOS technology from 0.25μm to 65nm: the state of the art

Abstract

The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools using which designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.

Design of Cascode-Based Transconductance Amplifiers with Low-Gain PVT Variability and Gain Enhancement Using a Body-Biasing Technique

“…So, despite the increase of transconductance with scaling, the intrinsic gain is reduced [1]. This is illustrated in [2]. The temperature variation leads to a decrease in both the carrier mobility and the threshold voltage.…”

“…In regards to the latter, it may decrease from 2 mV up to 4 mV for every 1º C rise [3]. These factors will have a direct effect on the transconductance of a transistor, as seen in (2). Also, process corners refer to the variation of fabrication parameters used in applying an integrated circuit design to a wafer.…”

Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

“…Nevertheless, as feature sizes scale down in deep submicron CMOS technologies, the transistor's intrinsic gain factor g m /g ds has decreased continuously [11][12][13] up to values in the range of only 5-10 for minimum length devices. Table 1 shows the evolution of the CMOS technology and the key parameters.…”

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

“…However, if a low price is the aim, the best choice is the use of CMOS technology. The designer simultaneously benefits from the advantages of downscaling which allows for reducing the power consumption, improving the maximum operation frequency and obtaining more compact designs [1,2].…”