RFTL: improving performance of selective caching-based page-level FTL through replication

Mativenga, Ronnie; Paik, Joon Young; Kim, Young-Jae; Lee, Jung‐Hee; Chung, Tae Sun

doi:10.1007/s10586-018-2824-5

Cited by 14 publications

(14 citation statements)

References 11 publications

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“…When fresh pages run-out, read/write operations are delayed while the system claims for the victim blocks with invalidated pages, allowing the for long GC processes which also poses more threat to the limited lifespan (erase cycles) of flash memory. Thus, block erase and page write operations are major factors effecting the low performance of flash memory [16], [34]. Table 1 shows that the latency of flash memory writes ae nearly 2000µs compared to the 1µs latency of PCM.…”

Section: B Motivationmentioning

confidence: 99%

“…Given that DRAM is volatile (Table 1) and expensive with limited scalability to store the entire page-mapping image for large scale SSDs. FSSDs (DRAM+Flash) employing selective-page-level mapping FTLs [16] always suffer from cache miss penalty. This is due to the fetch operations on flash for the request location and its corresponding data that may take longer than expected (penalty) because of the several reasons.…”

Section: B Motivationmentioning

confidence: 99%

“…PhaseFTL manages read/write requests via a selective-pagelevel mapping scheme (PMS) [16], [34]. This entire mapping image is located in PCM and is used to temporarily load and offload frequently accessed translation entries into the cached mapping table located in DRAM for faster address translations.…”

Section: ) Phaseftl Mapping Tablementioning

confidence: 99%

“…To serve all incoming I/O requests, SSDs have a controller that manages all the activities between host and user data in storage. It is comprises of a system software module called a Flash Translation Layer (FTL) [16], [17]. FTL's major roles includes (i) logical-to-physical address translation, (ii) wear-leveling techniques and (iii) garbage collection policy for maintaining and sustaining free SSD space, which only applies to FSSDs and not to PSSDs.…”

Section: Introductionmentioning

confidence: 99%

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ExTENDS: Efficient Data Placement and Management for Next Generation PCM-Based Storage Systems

et al. 2019

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Although flash memory solid state drives (FSSDs) outperform traditional hard disk drives (HDDs), their performance still fails to cope up with the perennial doubling speeds of microprocessors, regardless of the available high bandwidth. To alleviate this bottleneck, many semiconductor companies, such as Intel, Micron, Samsung, and Hynix have already recently manufactured faster and more scalable non-volatile memory (NVM) technology as main memory but none so far have publicly announced their implementation or production of a full NVM Phase Change Memory SSD (PCM-SSD). Considering implementing NVM-PCM as secondary memory, we can build a future PCM-SSD (PSSD) to replace the slow traditional FSSD. However, a careful design, especially for the controller is essential to hide and manage PCM endurance constraints, in-place-updates ability, bit-addressability and enabling it to appear as a block device to the host as their predecessors (HDD and FSSD) do. In this paper, we propose implementing ExTENDS, a hardware assumption of NVM-PCM instead of the NVM-flash memory as our future secondary/persistent memory in storage systems. We further present a PCM file translation layer (PhaseFTL) that can efficiently manage address translations from a host file system to PCM while hiding PCM constrains and allowing the PCM blocks to wear down evenly. Moreover, PhaseFTL can efficiently manipulate the bit-addressability and in-place-update feature of PCM. Our experimental results shows that our proposed PSSD can improve overall SSD performance throughput by an average of 69% compared to traditional FSSDs.

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Section: B Motivationmentioning

confidence: 99%

Section: B Motivationmentioning

confidence: 99%

Section: ) Phaseftl Mapping Tablementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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ExTENDS: Efficient Data Placement and Management for Next Generation PCM-Based Storage Systems

et al. 2019

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“…An operation of erase is conducted at the unit of a block, which consists of multiple pages and can match up to 1.5ms. On the contrary, a page is the unit, which is where operations of read and write are conducted, can match up to about 80 µs and 200 µs continuously [3]. However, NAND flash memory has a feature of hardware that a page is erased before being written in the equal location, and this is called operation of erase-before-write (out-of-place-update) [4].…”

Section: Introductionmentioning

confidence: 99%

DSFTL: An Efficient FTL for Flash Memory Based Storage Systems

et al. 2020

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Flash memory is widely used in solid state drives (SSD), smartphones and so on because of their non-volatility, low power consumption, rapid access speed, and resistance to shocks. Due to the hardware features of flash memory that differ from hard disk drives (HDD), a software called FTL (Flash Translation Layer) was presented. The function of FTL is to make flash memory device appear as a block device to its host. However, due to the erase before write features of flash memory, flash blocks need to be constantly availed through the garbage collection (GC) of invalid pages, which incurs high-priced overhead. In the previous hybrid mapping schemes, there are three problems that cause GC overhead. First, operation of partial merge causes more page copies than operation of switch merge. However, many authors just concentrate on reducing operation of full merge. Second, the availability between a data block and a log block makes the space availability of the log block lower, and it also generates a very high-priced operation of full merge. Third, the space availability of the data block is low because the data block, which has many free pages, is merged. Therefore, we propose a new FTL named DSFTL (Dynamic Setting for FTL). In this FTL, we use many SW (sequential write) log blocks to increase operation of switch merge and to decrease operation of partial merge. In addition, DSFTL dynamically handles the data blocks and log blocks to reduce the operations of erase and the high-priced operation of full merge. Additionally, our scheme prevents the data block with many free pages from being merged to increase the space availability of the data block. Our extensive experimental results prove that our proposed approach (DSFTL) reduces the count of erase and increases the operation of switch merge. As a result, DSFTL decreases the garbage collection overhead.

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Uniform scheduling of interruptible garbage collection and request IO to improve performance and wear-leveling of SSDs

et al. 2022

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RFTL: improving performance of selective caching-based page-level FTL through replication

Cited by 14 publications

References 11 publications

ExTENDS: Efficient Data Placement and Management for Next Generation PCM-Based Storage Systems

ExTENDS: Efficient Data Placement and Management for Next Generation PCM-Based Storage Systems

DSFTL: An Efficient FTL for Flash Memory Based Storage Systems

Uniform scheduling of interruptible garbage collection and request IO to improve performance and wear-leveling of SSDs

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