Rigel

Kelm, John H.; Johnson, D.; Johnson, Matthew; Crago, Neal; Tuohy, William; Mahesri, Aqeel; Lumetta, Steven S.; Frank, Matthew I.; Patel, Sanjay J.

doi:10.1145/1555754.1555774

Cited by 104 publications

(10 citation statements)

References 25 publications

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“…Over the MSI protocol, the Exclusive state has the added advantage of avoiding invalidation traffic on write hits. For scalability, we assume a directory protocol [Lenoski et al 1992]. Given our shared (inclusive) L2 cache-based multicore, we assume a directory entry per L2 cache line, referred to as an in-cache directory [Censier and Feautrier 1978].…”

Section: Mesimentioning

confidence: 99%

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

Komuravelli

Adve

Chou

2014

ACM Trans. Archit. Code Optim.

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Cache coherence is an integral part of shared-memory systems but is also widely considered to be one of the most complex parts of such systems. Much prior work has addressed this complexity and the verification techniques to prove the correctness of hardware coherence. Given the new multicore era with increasing number of cores, there is a renewed debate about whether the complexity of hardware coherence has been tamed or whether it should be abandoned in favor of software coherence. This article revisits the complexity of hardware cache coherence by verifying a publicly available, state-of-the-art implementation of the widely used MESI protocol, using the Murϕ model checking tool. To our surprise, we found six bugs in this protocol, most of which were hard to analyze and took several days to fix. To compare the complexity, we also verified the recently proposed DeNovo protocol, which exploits disciplined software programming models. We found three relatively easy to fix bugs in this less mature protocol. After fixing these bugs, our verification experiments showed that, compared to DeNovo, MESI had 15X more reachable states leading to a 20X increase in verification (model checking) time. Although we were eventually successful in verifying the protocols, the tool required making several simplifying assumptions (e.g., two cores, one address). Our results have several implications: (1) they indicate that hardware coherence protocols remain complex;(2) they reinforce the need for protocol designers to embrace formal verification tools to demonstrate correctness of new protocols and extensions; (3) they reinforce the need for formal verification tools that are both scalable and usable by non-expert; and (4) they show that a system based on hardware-software co-design can offer a simpler approach for cache coherence, thus reducing the overall verification effort and allowing verification of more detailed models and protocol extensions that are otherwise limited by computing resources.

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Section: Mesimentioning

confidence: 99%

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

Komuravelli

Adve

Chou

2014

ACM Trans. Archit. Code Optim.

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“…Tilera [20] and Rigel [10] support a standard multithreading programming model, thus providing the programmer with the maximum (known) flexibility. This programming model can be applied to any kind of parallel algorithm.…”

Section: Related Workmentioning

confidence: 99%

“…As for the hardware, a cache coherence protocol must be implemented, in order to support the shared memory assumption of the multithreading programming model. Tilera [20] employs a Dynamic Distributed Cache (DDC), but its scalability is still not proven for the 1000-core systems similar to Rigel [10]. Rigel implements a 1000-core accelerator, but the coherency of its caches is maintained by software.…”

Section: Related Workmentioning

confidence: 99%

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A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching

Lee

et al. 2012

Proceedings of the 9th Conference on Computing Frontiers

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Massively Parallel Processing Arrays (MPPA) constitute programmable hardware accelerators that excel in the execution of applications exhibiting Data-Level Parallelism (DLP). The concept of employing such programmable accelerators as sidekicks to the more traditional, general-purpose processing cores has very recently entered the mainstream; both Intel and AMD have introduced processor architectures integrating a Graphics Processing Unit (GPU) alongside the main CPU cores. These GPU engines are expected to play a pivotal role in the espousal of General-Purpose computing on GPUs (GPGPU). However, the widespread adoption of MPPAs, in general, as hardware accelerators entails the effective tackling of some fundamental obstacles: the expressiveness of the programming model, the debugging capabilities, and the memory hierarchy design. Toward this end, this paper proposes a hardware architecture for MPPA that adopts an event-driven execution model. It supports dynamic task scheduling, which offers better expressiveness to the execution model and improves the utilization of processing elements. Moreover, a novel module-level prefetching mechanism -enabled by the specification of the execution model -hides the access time to memory and the scheduler. The execution model also ensures complete encapsulation of the modules, which greatly facilitates debugging. Finally, the fact that all associated inputs of a module are explicitly known can be exploited by the hardware to hide memory access latency without having to resort to caches and a cache Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. coherence protocol. Results using a cycle-level simulator of the proposed architecture and a variety of real application benchmarks demonstrate the efficacy and efficiency of the proposed paradigm.

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“…The Rigel [65] architecture also manages cache-coherence under software control. The processor is organized in clusters, with 8 cores per cluster, and features a shared "cluster cache" -L1 cache.…”

Section: Software Managed Coherencementioning

confidence: 99%

Architectural support for software-guided energy reduction of manycore communication

Papaefstathiou¹,

Παπαευσταθίου²

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At the beginning of the 21st century, the processor industry made a fundamentalshift towards multicore architectures, in order to address the diminishingreturns in single-thread performance with increasing transistor counts, and in orderto overcome the severe power problems of clock frequency scaling. Semiconductortechnology trends indicate that now the era of power- and energy-constrainedmanycore architectures has come. Technology projections show that the energyconsumed by data movement and communication will dominate the correspondingbudget of future computing systems; thus, unnecessary data movements willsubtract significant energy margin from computations.The most popular communication model for multi-core and many-core architecturesis shared-memory. Threads or processes that run concurrently on differentcores communicate and exchange data by accessing the same global memory locations.However, accesses to off-chip memory are slow and, thus, processor designsutilize a hierarchy of faster on-chip memories to improve the speed of memory operations.Memory hierarchies today are based on two dominant schemes: (i) multilevelcoherent caches, and (ii) software-managed local memories (scratchpads).Caches manage the memory hierarchy transparently, using hardware replacementpolicies, and communication happens implicitly, with cache-coherence protocolsthat provoke data transfers between caches. Scratchpad memories are controlledby the programmer or the runtime software, and communication happens explicitly,through programmable DMA engines that perform the data transfers.This thesis proposes architectural support in the memory hierarchy to enablethe software to control data locality; we design programmable hardware primitivesthat allow runtime software to orchestrate communication and reduce the associatedenergy consumption.We demonstrate a hybrid cache/scratchpad memory hierarchy that providesunified hardware support for both implicit communication, via cache-coherence,and explicit communication, via fast virtualized inter-processor communicationhardware primitives. We also introduce the Epoch-based Cache Management(ECM), which allows software to assign priorities to cache-lines, in order to guidethe cache replacement policy, and, in effect, to manage locality. Moreover, wedesign the Explicit Bulk Prefetcher (EBP), a programmable prefetch engine thatallows software to accurately prefetch data ahead of time, in order to hide memory latency and improve cache locality. Furthermore, we propose a set of hardwareprimitives for Software Guided Coherence (SGC) in non-cache-coherent systems,in order to allow runtime software to orchestrate the fetching of the most up-todateversion of data from the appropriate cache(s) and maintain coherence at thesoftware object granularity.We evaluate our proposed hardware primitives by comparing them againstdirectory-based cache-coherence with hardware prefetching. Our experimental resultsfor explicit communication show that we can improve performance by 10% to40%, and at the same time reduce the energy consumption of on-chip communicationby 35% to 70% owing to significant reduction in on-chip traffic, by factors of2 to 4. Moreover, we exploit a task-based programming system to guide hardware,and show that our proposed hardware primitives in cache-coherent systems (ECM,EBP) improve performance by an average of 20%, inject 25% less on-chip trafficon average, and reduce the energy consumption in the components of the memoryhierarchy by an average of 28%. Our hardware support for non-cache-coherent systems(ECM, SGC) improves performance by an average of 14%, injects 41% lesson-chip traffic on average, and reduces the energy consumption in the componentsof the memory hierarchy by an average of 44%.

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Rigel

Cited by 104 publications

References 25 publications

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching

Architectural support for software-guided energy reduction of manycore communication

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