Rigorous simulation of exposure over nonplanar wafers

Erdmann, Andreas; Kalus, Christian K.; Schmoeller, Thomas; Klyonova, Yewgenija; Satō, Takashi; Endo, Ayako; Shibata, T.; Kobayashi, Yuuji

doi:10.1117/12.485390

Cited by 10 publications

(6 citation statements)

References 6 publications

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“…However, we can expect our model to predict the dominating effects of the wafer topography induced line scattering on the dose, linewidth and placement of features. A fully rigorous model of wafer topography induced scattering requires the simulation and superposition of light scattering effects for many directions of plane waves emerging from the exit pupil of the lens [4]. Such a modeling approach is very time and memory consuming -with typical computing times between several minutes and hours on a standard PC, whereas our simplified model only requires rigorous EMF simulation for two incidence directions.…”

Section: Simulation Procedures and Model Parametersmentioning

confidence: 99%

“…The exposure over patterned wafers can result in wafer topography effects such as reflective notching [3], resist footing [4], reduced efficiency of the bottom antireflective coating (BARC), and other exposure artifacts [5]. Nevertheless, the rigorous EMF modeling of light diffraction from topographic features on the wafer has attracted only little interest compared to the EMF mask modeling.…”

Section: Introductionmentioning

confidence: 98%

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Rigorous electromagnetic field simulation of two-beam interference exposures for the exploration of double patterning and double exposure scenarios

Erdmann

Evanschitzky

Fühner

et al. 2008

Optical Microlithography XXI

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The introduction of double patterning and double exposure technologies, especially in combination with hyper NA, increases the importance of wafer topography phenomena. Rigorous electromagnetic field (EMF) simulations of two beam interference exposures over non-planar wafers are used to explore the impact of the hardmask material and pattern on resulting linewidths and swing curves after the second lithography step. Moreover, the impact of the optical material contrast between the frozen and unfrozen resist in a pattern freezing process and the effect of a reversible contrast enhancement layer on the superposition of two subsequent lithographic exposures are simulated. The described simulation approaches can be used for the optimization of wafer stack configurations for double patterning and to identify appropriate optical material properties for alternative double patterning and double exposure techniques

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Section: Simulation Procedures and Model Parametersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Rigorous electromagnetic field simulation of two-beam interference exposures for the exploration of double patterning and double exposure scenarios

Erdmann

Evanschitzky

Fühner

et al. 2008

Optical Microlithography XXI

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“…and a simplified form would be I = (1-w 1 -w 2 )I 0 +w 1 I 1 +w 2 I 2 (4) where I 2 = <E 2 , E 2 * >.…”

Section: Fast Modelingmentioning

confidence: 99%

“…As a result, existing lithography modeling tools dedicated for OPC application cannot model the thin film topography effect mentioned above. The available tools for photolithography simulation with wafer topography, such as Synopsys' Sentaurus Lithography, adopt a rigorous approach that involves solving the Maxwell equations ( [4]). Although useful for detailed parameter studies and process development, such tools are unfit for mask synthesis applications due to their prohibitively long runtime.…”

Section: Introductionmentioning

confidence: 99%

Wafer topography proximity effect modeling and correction for implant layer patterning

Song

Shiely

Su³

et al. 2009

SPIE Proceedings

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Photolithography on reflective surfaces with topography can cause overexposure in some areas in the photoresist, resulting in undesired critical dimension (CD) variations in the printed patterns. Using bottom anti-reflective coatings (BARCs) will reduce the severity of the problem. However it is not a preferred solution in some situations due to added process complexity, such as the case of implant blocking layer patterning. This topography proximity effect (TPE) has been ignored in the mask synthesis flow for the 45nm and larger nodes due to its relatively small impact to the CDs. When the device critical length reaches 32nm and lower, the variations on the implant layer caused by underlying topography becomes more and more an issue and need to be addressed properly. In order to do that, simulation with nonplanar stack is required. The available tools for photolithography simulation with wafer topography, such as Synopsys' Sentaurus Lithography (S-Litho), usually adopt a rigorous approach based on the solution of the Maxwell equations and unsuitable for full chip optical proximity correction (OPC) due to their prohibitively long runtimes. A fast method for TPE modeling is needed to make full chip TPE correction feasible.In this paper, we propose a computationally fast approximate method that captures TPE well. It enables fast model calibration and full chip implant layer mask correction, and fits in the current OPC flows easily. We validate the method's effectiveness by comparing its simulation results with those produced by Sentaurus Lithography. We also show how it helps implant layer mask synthesis that takes TPE from previous layers into consideration.

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“…In this model, the intensity within the resist was determined under the assumption that the layer on the stack was homogeneous and parallel. The other model is the rigorous diffraction model [2]. In this model, incident light coming into the resist is simulated under the conditions that it is in a cone whose incident angle is that of numerical aperture and rigorously diffracted.…”

Section: Resist Footing Simulationmentioning

confidence: 99%

Resist footing variation and compensation over nonplanar wafer

et al. 2003

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This paper reports a problem regarding DUV lithography on topographical substrate and solution for obtaining desired CD control and resist pattern shape. In our experiment, large footing for 250 nm resist pattern was observed when the resist pattern was transferred over polysilicon step pattern of 175nm in height. This pattern error is not negligible regarding device performance. The exposure tool used was a KrF scanner of NA0.6. Resist was 500 nm thick with no ARC. Computer simulation was used to demonstrate the amount of footing. A non-rigorous diffraction model did not recreate the footing appearance at the poly-Si step. However, a rigorous diffraction model of incident light in a cone recreated the footing amount at the poly-Si step faithfully. In this simulation, optical distribution in the resist over the nonplaner wafer was solved by the FDTD method. Optical intensity at sidewall of the step differs between the two models. Experimental results as well as simulation results showed that the amount of the footing depended on a coherency factor of illumination. Larger coherency resulted in larger footing. In the case of a large coherency the illumination rays come from various directions to the wafer, and a large shadow area is likely to appear behind the steep step. As a consequence, optical behavior in the vicinity at the steep step has a strong impact on the resist footing. Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx Proc. of SPIE Vol. 5040 1523 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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Rigorous simulation of exposure over nonplanar wafers

Cited by 10 publications

References 6 publications

Rigorous electromagnetic field simulation of two-beam interference exposures for the exploration of double patterning and double exposure scenarios

Rigorous electromagnetic field simulation of two-beam interference exposures for the exploration of double patterning and double exposure scenarios

Wafer topography proximity effect modeling and correction for implant layer patterning

Resist footing variation and compensation over nonplanar wafer

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