RISC-V based virtual prototype: An extensible and configurable platform for the system-level

Herdt, Vladimir; Große, Daniel; Pieper, Pascal; Drechsler, Rolf

doi:10.1016/j.sysarc.2020.101756

Cited by 49 publications

(6 citation statements)

References 2 publications

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“…The former refers to the information low policies validation of designs implementing various aspects of the TLM-2.0 standard (core-interfaces, the base protocol, and coding styles) [3]. The latter refers to the information low policies validation of two real-word VP-based SoCs [24,36]. The analysis has been performed on a PC equipped with 24 GB RAM and an Intel core i7-8565U CPU running at 1.80 GHz.…”

Section: Resultsmentioning

confidence: 99%

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Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Goli¹,

Drechsler

2024

ACM Trans. Embed. Comput. Syst.

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Virtual Prototypes (VPs) at the Electronic System Level (ESL) are being increasingly adopted by the semiconductor industry and play an important role in modernizing the System-on-Chips (SoCs) design flow to raise design productivity and reduce time-to-market constraints. Due to their early availability and significantly faster simulation speed in comparison to Register Transfer Level (RTL) designs, VPs are used as reference models for lower levels of abstraction. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we present a novel VP-based dynamic information flow analysis approach at the ESL, consisting of three main phases which are run-time behavior extraction (in terms of transactions), transactions transformation, and security validation. The proposed approach empowers designers to validate the information flow policies of a given VP-based SoC against the most occurring security threat models which are information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including an extensive set of standard benchmarks and two real-world VP-based SoCs demonstrate the scalability and applicability of the proposed approach.

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Section: Resultsmentioning

confidence: 99%

“…In the second experiment, we consider the security scenario S2. To model this security scenario, we used the open-source RISC-V VP-based SoC [24] that is implemented in SystemC TLM-2.0. The VP is designed as an extensible and conigurable platform around a RISC-V RV32IM CPU core with a generic bus system SimpleBus.…”

Section: Case Study 2: Risc-v Vpmentioning

confidence: 99%

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Goli¹,

Drechsler

2024

ACM Trans. Embed. Comput. Syst.

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“…For system testing in the cloud, more general hardware models are needed, so that control applications can be executed on these models with their original machine code and address maps, as used on the real target. Such models have recently been developed; they are called virtual prototypes [12] and represent more advanced variants of the simulators that have been used for quite some time. We expect that certification credit for cloud-based system tests or HW/SW integration tests can be achieved if the software is executed in such a variant of virtual prototypes.…”

Section: System Test Scenariosmentioning

confidence: 99%

Complete Agent-driven Model-based System Testing for Autonomous Systems

Eder

Wei

Peleskã

2021

Electron. Proc. Theor. Comput. Sci.

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In this position paper, a novel approach to testing complex autonomous transportation systems (ATS) in the automotive, avionic, and railway domains is described. It is intended to mitigate some of the most critical problems regarding verification and validation (V&V) effort for ATS. V&V is known to become infeasible for complex ATS, when using conventional methods only. The approach advocated here uses complete testing methods on the module level, because these establish formal proofs for the logical correctness of the software. Having established logical correctness, system-level tests are performed in simulated cloud environments and on the target system. To give evidence that "sufficiently many" system tests have been performed with the target system, a formally justified coverage criterion is introduced. To optimise the execution of very large system test suites, we advocate an online testing approach where multiple tests are executed in parallel, and test steps are identified on-the-fly. The coordination and optimisation of these executions is achieved by an agentbased approach. Each aspect of the testing approach advocated here is shown to either be consistent with existing standards for development and V&V of safety-critical transportation systems, or it is justified why it should become acceptable in future revisions of the applicable standards.

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“…2) Dynamic IFT: We have implemented our dynamic IFT approach for security policy evaluation on top of the open source RISC-V VP [16,17] available at GitHub [18] that is implemented in SystemC TLM. For the evaluation we considered three different experiments.…”

Section: ) Static Iftmentioning

confidence: 99%

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

Rai

Garg

Pilato

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both-the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives-from systemlevel down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.1 Not requiring any changes to the EDA flows.

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RISC-V based virtual prototype: An extensible and configurable platform for the system-level

Cited by 49 publications

References 2 publications

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Complete Agent-driven Model-based System Testing for Autonomous Systems

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

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