RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures

Abstract

Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as the "memory wall" and severely limits the performance of a microprocessor. One of the most promising solutions is the "logic-in-memory" approach. It consists of merging memory and logic units, enabling data to be processed directly inside the memory itself. Here we propose an RISC-V framework that supports logic-in-memory operations. We substitute data memory with a circuit capable of storing data and of performing in-memory computation. The framework is based on a standard memory interface, so different logic-in-memory architectures can be inserted inside the microprocessor, based both on CMOS and emerging technologies. The main advantage of this framework is the possibility of comparing the performance of different logic-in-memory solutions on code execution. We demonstrate the effectiveness of the framework using a CMOS volatile memory and a memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in algorithm execution speed and a reduction in energy consumption.

Design and Evaluation of Open-Source Soft-Core Processors

“…In addition, only cores implemented in Verilog or the subset of System Verilog handled by Yosys were considered. RISC-V cores have a tremendous range in performance and complexity [9], from tiny 32-bit microcontrollers to out-of-order 64-bit application cores for data centers. Only the low end was studied here.…”

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

“…The proposed design described in Coluccio et al (2022) replaces the data memory with a circuit that is capable of storing data and performing calculations in memory, respectively. In this context, the authors propose a RISC-V framework that supports logic-in-memory operations.…”

“…Since the framework is based on a standard memory interface, different logic-in-memory architectures, based on both CMOS and emerging technologies, can practically be placed inside the microprocessor. In this article ( Coluccio et al, 2022 ), the efficiency of the framework is verified using a CMOS volatile memory and a memory based on a new emerging technology, race circuit logic.…”

A novel reduced instruction set computer-communication processor design using field programmable gate array

“…The VHDL-based RISC processor architecture is developed to minimize the execution time of the static code analysis [18]. The RISC architecture is used to embed the sensing system to reduce the size when implemented in the FPGA device [19]- [21]. The RISC processor is analyzed for single event transient fault for the possibility of multiple bit upsets by implementing in the FPGA [22]- [24].…”