RISPP: Rotating Instruction Set Processing Platform

Abstract-This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions. We describe a design flow to identify promising area, performance, and code-size tradeoffs. We study the effect of input/output constraints, register-file ports, and compiler transformations such as if-conversion. Our experiments show that, in most cases, the solutions with the highest performance are identified when the input/output constraints are removed. However, input/output constraints help our algorithms identify frequently used code segments, reducing the overall area overhead. Results for 11 benchmarks covering cryptography and multimedia are shown, with speed-ups between 1.7 and 6.6 times, code-size reductions between 6% and 72%, and area costs ranging between 12 and 256 adders for maximum speed-up. Our ILP-based approach scales well: benchmarks with basic blocks consisting of more than 1000 instructions can be optimally solved, most of the time within a few seconds.Index Terms-Application-specific instruction-set processors (ASIPs), custom instructions, customizable processors, extensible processors, integer linear programming (ILP), optimization algorithms.

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“…We hope to extend our approach to cover run-time reconfigurable processors [51] and heterogeneous multiprocessor systems [52].…”

Section: Discussionmentioning

confidence: 99%

CHIPS: Custom Hardware Instruction Processor Synthesis

Atasu

Özturan

Dündar

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, none of these approaches targets platforms exploiting dynamic reconfiguration of custom functional units. Recently, Bauer et al [2] have developed rotating instruction set processing platform that selects custom instructions at runtime. We [9] have earlier presented an efficient framework for runtime reconfiguration of custom instructions.…”

Section: Related Workmentioning

confidence: 99%

Runtime reconfiguration of custom instructions for real-time embedded systems

Huynh¹,

Mitra²

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-This paper explores runtime reconfiguration of custom instructions in the context of multi-tasking real-time embedded systems. We propose a pseudo-polynomial time algorithm that minimizes processor utilization through customization and runtime reconfiguration, while satisfying all the timing constraints. Our experimental infrastructure consists of Stretch customizable processor supporting runtime reconfiguration as the hardware platform and realistic embedded benchmarks as applications. We observe that runtime reconfiguration of custom instructions can help to reduce the processor utilization by up to 64%. The experimental results also demonstrate that our algorithm is highly scalable and achieves optimal or near optimal (3% difference) processor utilization.

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“…RISPP (Rotating Instruction Set Processing Platform) [4] is a recent architecture that offers a unique approach towards runtime customization. RISPP introduces the notion of atoms and molecules for custom instructions.…”

Section: Transparent Extensible Processorsmentioning

confidence: 99%

Runtime Adaptive Extensible Embedded Processors — A Survey

Huynh

Mitra

2009

Lecture Notes in Computer Science

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Abstract. Current generation embedded applications demand the computation engine to offer high performance similar to custom hardware circuits while preserving the flexibility of software solutions. Customizable and extensible embedded processors, where the processor core can be enhanced with application-specific instructions, provide a potential solution to this conflicting requirements of performance and flexibility. However, due to the limited area available for implementation of custom instructions in the datapath of the processor core, we may not be able to exploit all custom instruction enhancements of an application. Moreover, a static extensible processor is fundamentally at odds with highly dynamic applications where the custom instructions requirements vary substantially at runtime. In this context, a runtime adaptive extensible processor that can quickly morph its custom instructions and the corresponding custom functional units at runtime depending on workload characteristics is a promising solution. In this article, we provide a detailed survey of the contemporary architectures that offer such dynamic instruction-set support and discuss compiler and/or runtime techniques to exploit such architectures.

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RISPP: Rotating Instruction Set Processing Platform

Cited by 28 publications

References 0 publications

CHIPS: Custom Hardware Instruction Processor Synthesis

CHIPS: Custom Hardware Instruction Processor Synthesis

Runtime reconfiguration of custom instructions for real-time embedded systems

Runtime Adaptive Extensible Embedded Processors — A Survey

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