Robust Avalanche in 1.7 kV Vertical GaN Diodes With a Single-Implant Bevel Edge Termination

Xiao, Ming; Wang, Yifan; Zhang, Ruizhe; Song, Qihao; Porter, Matthew; Carlson, E.P.; Cheng, Kai; Ngo, Khai D. T.; Zhang, Yuhao

doi:10.1109/led.2023.3302312

Cited by 14 publications

(3 citation statements)

References 30 publications

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“…The carrier channel is 20~30 nm away from the device surface, easily inducing trapping at the device surface or in the heterostructure [6], [47]. In the GaN JFET, the peak E-field is at the edge termination (implantation-based, similar to [21], [48]); the high E-field in the active region is embedded at the p-n junction, which is far from (~1 µm) the device surface. In addition, due to the lower defect density in GaN epi layers grown on GaN substrate compared to those grown on Si [49], both surface and buffer trapping are largely suppressed.…”

Section: Discussion On Physical Mechanismmentioning

confidence: 99%

Dynamic R _ON Free 1.2-kV Vertical GaN JFET

Yang,

Zhang,

Wang

et al. 2024

IEEE Trans. Electron Devices

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Dynamic on-resistance (RON) or threshold voltage (VTH) instability caused by charge trapping is one of the most crucial reliability concerns of some GaN high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic RON and VTH stability of an industrial vertical GaN transistor-NexGen's 1200V/70mΩ fin-channel JFET, fabricated on 100 mm bulk GaN substrates. A circuit setup is deployed for the in-situ measurement of the dynamic RON under steady-state switching. The longer-term stability of RON and VTH is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no RON or VTH shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices towards power electronics applications. 1

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Section: Discussion On Physical Mechanismmentioning

confidence: 99%

Dynamic R _ON Free 1.2-kV Vertical GaN JFET

Yang,

Zhang,

Wang

et al. 2024

IEEE Trans. Electron Devices

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“…4 Fig. 5 compares the differential R ON,SP versus BV trade-off of the vertical GaN SJ diode with the state-of-the-art vertical GaN 1D diodes [21]- [30] and SiC SJ devices [4]- [6], as well as the 1D SiC/GaN limits and the GaN SJ limit [𝑅𝑅 𝑜𝑜𝑜𝑜,𝑠𝑠𝑠𝑠 = 4𝑤𝑤 𝑜𝑜 𝐵𝐵𝐵𝐵/ (𝜀𝜀𝜇𝜇 𝑜𝑜 𝐸𝐸 𝐶𝐶…”

Section: Introductionmentioning

confidence: 99%

1 kV Self-Aligned Vertical GaN Superjunction Diode

Ma,

Porter,

Qin

et al. 2024

IEEE Electron Device Lett.

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This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (BV) of 1100 V, a specific on-resistance (RON) of 0.4 mΩ·cm 2 , and a SJ drift-region resistance (Rdr) of 0.13 mΩ·cm 2 . The device also exhibits good thermal stability with BV retained over 1 kV and RON dropped to 0.3 mΩ·cm 2 at 125 o C. The trade-off between BV and Rdr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide-and ultra-wide bandgap semiconductors. 1

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“…and breakdown voltage (BV) still have room for more investigation before approaching theoretical limit of GaN materials. To tackle this challenge, studies based on edge termination technologies have been made including field plates [3], ion implantation [4], field rings [5], p-type junction termination extension [6], reverse p-n junction termination [7], etc. Edge termination helps make the electric field more evenly supported by the drift layer and the BV can be increased [8], such that Si 3 N 4 is set under anode metal edge to suppress the strong electric field at contact periphery [9].…”

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confidence: 99%

1.43 kV GaN-based MIS Schottky barrier diodes

Huang,

Chu,

Wang

et al. 2024

J. Phys. D: Appl. Phys.

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In this letter, we report on a quasi-vertical GaN-based metal-insulator-semiconductor (MIS) Schottky barrier diode with an insertion of 2 nm thick Al2O3 dielectric layer. It shows a turn-on voltage of 0.7 V, a specific on-resistance of 3.5 mΩ·cm2, and a high on/off current ratio of 1011. The proposed structure enables a breakdown voltage of 1430 V, rendering a Baliga’s power figure-of-merit of 0.58 GW·cm-2. The enhanced performance is attributed to defect-related leakage can be suppressed and the direct tunneling process dominates at the MIS-based Schottky contact interface.

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Robust Avalanche in 1.7 kV Vertical GaN Diodes With a Single-Implant Bevel Edge Termination

Cited by 14 publications

References 30 publications

Dynamic R _ON Free 1.2-kV Vertical GaN JFET

Dynamic R _ON Free 1.2-kV Vertical GaN JFET

1 kV Self-Aligned Vertical GaN Superjunction Diode

1.43 kV GaN-based MIS Schottky barrier diodes

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Robust Avalanche in 1.7 kV Vertical GaN Diodes With a Single-Implant Bevel Edge Termination

Cited by 14 publications

References 30 publications

Dynamic R ON Free 1.2-kV Vertical GaN JFET

Dynamic R ON Free 1.2-kV Vertical GaN JFET

1 kV Self-Aligned Vertical GaN Superjunction Diode

1.43 kV GaN-based MIS Schottky barrier diodes

Contact Info

Product

Resources

About

Dynamic R _ON Free 1.2-kV Vertical GaN JFET

Dynamic R _ON Free 1.2-kV Vertical GaN JFET