Robust Clock Tree Routing in the Presence of Process Variations

Padmanabhan, Uday; Wang, J.M.; Hu, Jiang

doi:10.1109/tcad.2008.925776

Cited by 16 publications

(4 citation statements)

References 30 publications

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“…If the ∆ delay (Y rcw ) or ∆ delay (Y cw ) becomes larger than the corresponding A rcw or A cw , we can use TBC, which will reduce the delay variation and improve WNS. Alternatively, we can also intentionally route the wires over multiple layers during the physical implementation stages so as to create critical paths which has less BEOL variations as already discussed in [17] [19].…”

Section: B Resultsmentioning

confidence: 99%

Improved signoff methodology with tightened BEOL corners

Chan

Dobre

Kahng

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Abstract-To ensure functional correctness, conventional chip implementation methodology signs off the SOC design at extreme process, voltage and temperature (PVT) conditions. At the 20nm node and beyond, the back end of line (BEOL) layers have become major sources of variation, which must be accounted for by signoff at various BEOL corners. Conventional signoff methodology uses extreme BEOL corners, in which all BEOL layers are skewed to the worst-case condition (e.g., all BEOL layers have the worst parasitic capacitance). However, such a BEOL condition is very pessimistic because the probability of having all BEOL layers skew towards the worst-case condition simultaneously is extremely small. Such pessimism results in longer chip implementation schedules and poorer design quality. In this paper, we propose a signoff methodology with tightened BEOL corners to recover the pessimism incurred by the conventional BEOL corners. This approach is based on the observation that most timing-critical paths use different BEOL layers. When the variations of BEOL layers are not fully correlated, the BEOL-induced timing variation is much smaller due to averaging of random variations. Our experimental results show that by using tightened BEOL corners, we can reduce timing-violation paths by up to 100% and improve the WNS and TNS by up to 101ps and 53ns, respectively.

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Section: B Resultsmentioning

confidence: 99%

Improved signoff methodology with tightened BEOL corners

Chan

Dobre

Kahng

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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“…We scan in 5 (=4 + 1) to the delay value of ADB ref for one testing flow. Then, in the subsequent two testing flows, we scan in 6 unless the value has reached Max syn (Min syn ). Otherwise, the corresponding synchronizer is deemed to be faulty.…”

Section: A Scan-chain Architecture and The Proposed Algorithmmentioning

confidence: 99%

A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

Kao

Tsai

Chang

2015

IEEE Trans. VLSI Syst.

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Clock skew minimization that is an important issue in very large scale integration design has become difficult due to the presence of process, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable discussion. The basic idea of the PST architecture is to minimize the clock skew dynamically. Unlike most previous works that have focused on the implementation and the performance issues of a PST architecture, this paper focuses on the testing issues of a PST architecture. However, testing the variation tolerance ability of the PST architecture is difficult because the clock skew does not directly affect the functionality of a design. In this paper, we propose an efficient fault model considering the physical limitation of the devices for the PST architecture. In addition, we propose some novel structures to detect the manufacturing faults and increase the robustness of a PST architecture. Our experiment shows that with a little increase in overhead, we can achieve robustness.

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“…Various works have proposed clock network structures in order to mitigate or tolerate the clock-skew variation. The structures are roughly classified into a variation-aware clock tree structure (e.g., Wason et al [2007] and Padmanabhan et al [2008]), a non-tree structure by inserting links (e.g., Rajaram et al [2006], Yang et al [2007], and Lam et al [2005]) and clock mesh network (e.g., Restle et al [2001], Cho et al [2010], Guthaus et al [2012], Venkataraman et al [2010], Rajaram and Pan [2010], Chakrabarti et al [2012], and Lu et al [2012]). Among the structures, the clock mesh network offers the highest tolerance to the delay variation since the mesh grid contains multiple paths from the clock source to every clock sink, thus the delay variation in a path is compensated by the delay of another path(s).…”

Section: Introductionmentioning

confidence: 99%

Integrated Resource Allocation and Binding in Clock Mesh Synthesis

Kang

Kim

2014

ACM Trans. Des. Autom. Electron. Syst.

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The clock distribution network in a synchronous digital circuit delivers a clock signal to every storage element, that is, clock sink in the circuit. However, since the continued technology scaling increases PVT (processvoltage-temperature) variation, the increase of clock-skew variation is highly likely to cause performance degradation or system failure at runtime. Recently, to mitigate the clock-skew variation, many researchers have taken a profound interest in the clock mesh network. However, though the structure of the clock mesh network is excellent in tolerating timing variations, it demands significantly high power consumption due to the use of excessive mesh wire and buffer resources. Thus, optimizing the resources required in the mesh clock synthesis while maintaining the variation tolerance is crucially important. The three major tasks that greatly affect the cost of the resulting clock mesh are: (1) mesh segment allocation, (2) mesh buffer allocation and sizing, and (3) clock sink binding to mesh segments. Previous clock mesh optimization approaches solve the three tasks sequentially, one by one at a time, to manage the runtime complexity of the tasks at the expense of losing the quality of results. However, since the three tasks are tightly interrelated, simultaneously optimizing all three tasks is essential, if the runtime is ever permitted, to synthesize an economical clock mesh network. In this work, we propose an approach that is able to tackle the problem in an integrated fashion by combining the three tasks into an iterative framework of incremental updates and solving them simultaneously to find a globally optimal allocation of mesh resources while taking into account the clock-skew tolerance constraints. The core parts of this work are a precise analysis on the relation among the resource optimization tasks and an establishment of a mechanism for effective and efficient integration of the tasks. In particular, to handle the runtime problem, we propose a set of speedup techniques, that is, modeling the RC circuit for eliminating redundant matrix multiplications, exploiting a sliding-window scheme, and quickly estimating the buffer sizing effect, which are fitted into our context of fast clock-skew estimation in mesh resource optimization as well as an invention of early decision policies. Through extensive experiments with benchmark circuits, it is shown that our proposed clock mesh synthesizer is able to reduce the worst-case clock skew, total mesh wirelength, total size of mesh driving buffers, and total clock mesh power consumption including short-circuit power by 25.0%, 13.2%, 10.9%, and 11.0% on average compared to that produced by the best-known clock mesh synthesis method (MeshWorks), respectively. ACM Reference Format:Minseok Kang and Taewhan Kim. 2014. Integrated resource allocation and binding in clock mesh synthesis.

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Robust Clock Tree Routing in the Presence of Process Variations

Cited by 16 publications

References 30 publications

Improved signoff methodology with tightened BEOL corners

Improved signoff methodology with tightened BEOL corners

A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

Integrated Resource Allocation and Binding in Clock Mesh Synthesis

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