Robust design of CMOS amplifiers oriented to settling‐time specification

Abstract

In this paper, we propose a new approach for the robust design of complementary metal-oxide-semiconductor amplifiers based on settling-time specifications. The approach is based on the definition of the separation factors and on the analysis of their role in the settling time. We define a design strategy for being certain that an OTA satisfies the settling-time constraint under any statistical variation of process or design parameters. The proposed strategy is applied to the transistor level design of a two-stage amplifier and a three-stage one. Simulation results, in good agreement with theory, confirm the validity of the proposed approach. Copyright

Bessel‐like compensation of three‐stage operational transconductance amplifiers

“…which, for a given settling error, , represents the settling time of the amplifier under test, t s , normalized by the settling time of an ideal single-pole amplifier with the same GBW. 28 By inspection of Table 1, it is apparent that the NST of the settling time-oriented amplifiers is lower than that of any other amplifier of the first group. Moreover, in the group of the settling time-oriented design, the NST is below unity, thus meaning that these OTAs exhibit a settling time faster than that of a single-pole amplifier with the same GBW, which, usually, is a feature contrary to common-sense expectation.…”

Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints

“…To minimize the small-signal settling-time we followed the procedure in [22]. Specifically, we identified the separation factors as…”

Classification and Design Space Exploration of Low-Power Three-Stage Operational Transconductance Amplifier Architectures for Wide Load Ranges

“…This is not a very serious limitation, however, since OTAs that rely on pole-zero cancellation usually achieve this cancellation at a specific value of the load capacitor. Any change in the load capacitor makes the OTA return to being a three-pole system and justifies the use of κ [64].…”

“…The rest of this paper is organized as follows: Section 2 starts by examining control-theoretic issues common to all three-stage OTAs where it is noted that the current approach of designing the amplifier for a target phase margin [3,33,[43][44][45][46]48] without regard to other stability metrics can lead to a design that performs sub-optimally [62,64] and is wasteful of power. With the common challenges noted and the design procedure of optimizing the response for settling time instead is outlined, the proposed figure of merit for architecture comparison is explained in detail.…”