2010
DOI: 10.1116/1.3517718
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Robust estimation of line width roughness parameters

Abstract: Estimation of line width roughness (LWR) parameters is necessary for semiconductor process optimization, comparison of next-generation lithography processes as well as device performance simulation. According to previous studies [V. Constantoudis et al., J. Vac. Sci. Technol. B 21, 1019 (2003); J. Vac. Sci. Technol. B 22, 1974 (2004)], a complete description of LWR can be provided by three parameters: root-mean square roughness (σ), correlation length (ξ), and roughness exponent (α). However, the primary chall… Show more

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Cited by 7 publications
(7 citation statements)
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“…1(b) depicts the profiles of the two coupled lines obtained with ∆ℓ = 5 µm. These profiles are in good agreement with real profiles measured with scanning electron microscopes (see, e.g., [2]). It is important to point out that, besides this alternative proposed approach, state-of-the-art models can be fitted in the proposed simulation framework as well.…”
Section: B Line-edge Roughness Modelsupporting
confidence: 88%
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“…1(b) depicts the profiles of the two coupled lines obtained with ∆ℓ = 5 µm. These profiles are in good agreement with real profiles measured with scanning electron microscopes (see, e.g., [2]). It is important to point out that, besides this alternative proposed approach, state-of-the-art models can be fitted in the proposed simulation framework as well.…”
Section: B Line-edge Roughness Modelsupporting
confidence: 88%
“…LER is introduced by several sources in the manufacturing process, including photolitographic mask uncertainties and chemical properties of resist [2]. Owing to the inherent random nature of the problem, several statistical approaches have been proposed for the determination of the resistance and/or capacitance of on-chip lines [3]- [5].…”
Section: Introductionmentioning
confidence: 99%
“…Specifically, as the cross-sectional interconnect dimensions are reduced, a non-negligible impact of conductor edge roughness is found on the electrical performance of on-chip and nanoscale interconnects [2]- [4]. Line-edge roughness (LER) is the longitudinal variation of the conductor edges and has many sources, including mask roughness and statistical phenomena like resist diffusion and chemical etching [5].…”
Section: Introductionmentioning
confidence: 99%
“…The approach is validated via the analysis of an inverted embedded microstrip (IEM) line in both the frequency and time domain. The statistical properties of LER are usually described by at least two relevant parameters [5]: the absolute standard deviation σ r of the conductor edge from its nominal crosssectional position, and the correlation length ∆ℓ along the direction of propagation z. Fig.…”
Section: Introductionmentioning
confidence: 99%
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