Robust signaling techniques for through silicon via bundles

Chillara, Krishna C.; Jang, Jin-Wook; Burleson, Wayne

doi:10.1145/1973009.1973089

Cited by 4 publications

(2 citation statements)

References 16 publications

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“…Serialization is one of the solutions for overcoming the aforementioned issues. Since TSVs can transfer data up to 40 Gb/s [10] [11], serializing the data and reducing the number of TSVs can help to improve the yield and fabrication cost of the system and reduce the area occupied by the TSVs. Fig.…”

Section: Cross Talkmentioning

confidence: 99%

Parallel vs. serial inter-plane communication using TSVs

Omam

Leblebici

Micheli

2014

2014 IEEE 5th Latin American Symposium on Circuits and Systems

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Section: Cross Talkmentioning

confidence: 99%

Parallel vs. serial inter-plane communication using TSVs

Omam

Leblebici

Micheli

2014

2014 IEEE 5th Latin American Symposium on Circuits and Systems

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“…At system level, it allows the integration of memory with logic, thus allowing larger memory at lower access times, addressing the memory bottleneck problem more efficiently. The inherent advantages of 3D ICs and their ability to go beyond Moore's Law make it more interesting to explore new designs based on 3D integration [1].…”

Section: Introductionmentioning

confidence: 99%

Structure optimization of through silicon via (TSV) interconnect as transmission channel for 3D integration

Rahman

Yan

Miao

et al. 2013

2013 5th IEEE International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications

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Through silicon via is the latest interconnect technology mainly targeted for 3-D integration. Though the technology is yet to be matured enough, but researchers from both academic and industries are putting their highest effort to make the best use of it. The different design parameter and structural geometry has a great effect on the performance of TSV. This paper is intended for modeling and optimization of different TSV geometry structure for higher performance based on 3D full wave simulation and circuit simulator. The TSV structures have been modeled and simulated using 3-D EM field simulator HFSS and circuit simulator ADS has been used to simulate the electrical circuit model of the structure. From the simulation result it is seen that the insertion loss varies minimum in cylindrical TSV. The simulation results also show that for same TSV parameters (height, diameter, and insulation gap) the cylindrical TSV performs better than that of other type of structure.

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3D/TSV-Enabling Technologies

Ismail

El-Rouby

2014

Analog Circuits and Signal Processing

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Three-dimensional (3D) integration is a promising alternative option to traditional two-dimensional (2D) planar chips. The 3D integration is mainly concerned with the communication infrastructure between different stacked dies of future multicore system-on-chip (SoC) and network-on-chip (NoC). Among several 3D integration technologies, the through silicon via (TSV) approach is the most promising one and therefore is the focus of the majority of 3D integration R&D activities. However, there are challenges that should be overcome before the production of TSV-based 3D integrated circuits (ICs) becomes possible, e.g., electrical modeling challenges, thermal and power challenges, technological challenges, design methodology challenges, and computer-aided design (CAD) tool development challenges. The manufacturability of TSV-based 3D-ICs is an important issue for realizing real 3D-ICs designs. 3D/TSV TechnologyThe small-scale production of integrated circuits (ICs) started in the early 1960s. The modern-day ICs may have billions of transistors. The functionality scales by reducing the size of the transistors and also by increasing the transistor count per unit area of the processor die. More transistors are added to processors with each technology node. System-on-chip (SoC) was introduced in order to integrate all the components on a single substrate. SoC has incredible functionality, having processor, digital logic, memory, embedded intelligence, and analog components on a single die. However, interconnect length is a critical issue for SoC due to increase in the chip dimensions. Mixed signal integration is another issue for present-day SoC as the noisy digital part cannot be placed in close proximity to the sensitive analog part. In addition to this, same technology node has to be followed for different components of SoC which may place stringent requirements on analog and radio frequency (RF) components. Three-dimensional (3D) integration with through silicon vias (TSVs) is, therefore, an obvious choice for mixed technology applications compared to SoC. In other words, increasing drive for the integration of different

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Robust signaling techniques for through silicon via bundles

Cited by 4 publications

References 16 publications

Parallel vs. serial inter-plane communication using TSVs

Parallel vs. serial inter-plane communication using TSVs

Structure optimization of through silicon via (TSV) interconnect as transmission channel for 3D integration

3D/TSV-Enabling Technologies

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