Robust system design with built-in soft-error resilience

Mitra, Subhasish; Seifert, N.; Zhang, M.; Shi, Qi; Kim, K.S.

doi:10.1109/mc.2005.70

Cited by 472 publications

(231 citation statements)

References 14 publications

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“…If the robustness of the system meets the safety requirement, the system passes the validation; else the robustness/safety is not adequate, so Phase 3 is activated to enhance the system robustness/safety. Phase 3 (fault-tolerant design and risk reduction): This phase is to develop a feasible riskreduction approach by fault-tolerant design, such as the schemes presented in [Austin, 1999;Mitra et al, 2005;Rotenberg, 1999;Slegel et al, 1999;], to improve the robustness of the critical components identified in Phase 2. The enhanced version then goes to Phase 2 to recheck whether the adopted risk-reduction approach can satisfy the safety/robustness requirement or not.…”

Section: Safety Validation and Risk Reduction Processmentioning

confidence: 99%

Vulnerability Analysis and Risk Assessment for SoCs Used in Safety-Critical Embedded Systems

Chen¹,

Juang²

2012

Embedded Systems - Theory and Design Methodology

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Section: Safety Validation and Risk Reduction Processmentioning

confidence: 99%

Vulnerability Analysis and Risk Assessment for SoCs Used in Safety-Critical Embedded Systems

Chen¹,

Juang²

2012

Embedded Systems - Theory and Design Methodology

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“…Currently research efforts include more sophisticated approaches than simple replication. [18] reuses testing circuitry for error detection and correction and [17] extends hardware with built-in soft error resilience which is able to detect and correct soft errors and even to predict a soon hardware failure. The hardware design presented in [26] on-the-fly replicates executed instructions.…”

Section: Related Workmentioning

confidence: 99%

AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware

Fetzer

Schiffel

Süßkraut

2009

Lecture Notes in Computer Science

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Abstract. In the future, we expect commodity hardware to be used in safety-critical applications. However, in the future commodity hardware is expected to become less reliable and more susceptible to soft errors because of decreasing feature size and reduced power supply. Thus, software-implemented approaches to deal with unreliable hardware will be needed. To simplify the handling of value failures, we provide failure virtualization in the sense that we transform arbitrary value failures caused by erroneous execution into fail-stop failures. The latter ones are easier to handle. Therefore, we use the arithmetic AN-code because it provides very good error detection capabilities. Arithmetic codes are suitable for the protection of commodity hardware because guarantees can be provided independent of the executing hardware. This paper presents the encoding compiler EC-AN which applies AN-encoding to arbitrary programs. According to our knowledge, this is the first in software implemented complete AN-encoding. Former encoding compilers either encode only small parts of applications or trade-off safety to enable complete AN-encoding.

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“…A single event upset (SEU) does not occur unless the SET can survive the circuit masking effects and is captured by a clock edge into a sequential element. The SET can be eliminated by electrical masking, logic masking and temporal masking [9,10].…”

Section: An Environment-based Probabilistic Soft Error Modelmentioning

confidence: 99%

“…For a broad tutorial on this subject one may refer to a recent paper [14]. When neutrons strike silicon, any of more than 100 different nuclear reactions can be generated [9]. Accurate measurement of the neutron flux and its energy distribution are first considerations for estimating neutron-induced error rates.…”

Section: Introductionmentioning

confidence: 99%