Robust Wafer-Level Thin-Film Encapsulation of Microstructures using Low Stress PECVD Silicon Carbide

Abstract

This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface-and thin-SOI microstructures that included microcavities, RF switches and various accelerometers. Advantages of our technique are its versatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses related design aspects for large-area MEMS and demonstrates the encapsulation results. Successfully encapsulation of device geometries as large as 955x827.m2 has been achieved.

PECVD silicon carbide surface micromachining technology and selected MEMS applications

“…The Fig. 10 Top view of the fabricated RF electrostatic switch [9,11] Fig. 13 Top view of a released lateral accelerometer [12] Int J Adv Eng Sci Appl Math measured output characteristics of the PECVD SiC vertical accelerometer is presented in Fig.…”

“…Besides, this packaging approach enables a smaller footprint and chip thickness compared to other wafer-level packaging (WLP) techniques employing wafer bonding [14,15]. Also this encapsulation process can impart functionality by integrating additional z-axis electrodes [9,11] for devices requiring vertical detection or actuation, implemented in our electrostatic RF MEMS switch described in Sect. 3.3.…”

“…The structure and design of some selected MEMS devices employing capacitive detection and electrostatic actuation, namely, pressure sensor [8], accelerometers [12] and RF switch [11] together with wafer-level thin-film packaging [9,10], are presented below. Figure 2 presents the schematic structure of a capacitive absolute pressure sensor and the resultant cross-section after device fabrication.…”

“…Moreover, this approach enables a smaller footprint and chip thickness compared to other WLP techniques employing wafer bonding [14,15]. Here, only the feasibility of obtaining such an encapsulation using the generic process is discussed and a more detailed treatment is reported elsewhere [9,10]. As an example, the RF switch discussed in the following section has been designed using the packaging concept described here.…”

“…An overview of selected MEMS applications realised in this technology at the DIMES Technology Center (DTC) of TU Delft is provided. Presented MEMS examples include-an absolute pressure sensor [8], wafer-level thin-film packaging [9,10], RF switch [9,11] and accelerometers [12]. Key features of the proposed technology are its ability to withstand certain harsh environments, versatility in fabricating a wide range of MEMS, reliable and cost-effective batch manufacturability, CMOS compatibility, smaller footprint and chip thickness than bulk micromachined counterparts [13,14] as well as reduced process complexity.…”