Robustness Analysis of 3–2 Adder Compressor Designed in 7-nm FinFET Technology

Andrade, Gerson; Silva, Matheus; Schneider, Cinthia; Paim, Guilherme; Bampi, Sérgio; Costa, Eduardo; Zimpeck, Alexandra L.

doi:10.1109/tcsii.2023.3241197

Cited by 2 publications

(1 citation statement)

References 16 publications

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“…The mean (m), standard deviation (σ) and normalized standard deviation (σ/μ) % for the FinFET domino buffer circuit are used to estimate the degree of uncertainty for various approaches as shown in table 7. The circuit level technique with least variability impact is considered the best choice for designing digital logic circuits [31][32][33]. The proposed INDIDO approach for FinFET buffer circuit has reduced value of uncertainty at 16 nm FinFET technology node, making it more reliable, as demonstrated by analysis above.…”

Section: Variability and Noise Analysis Of Domino Buffer Circuitsmentioning

confidence: 92%

INDIDO: A novel low-power approach for domino logic circuits

Mushtaq,

Akram,

Prasad

et al. 2024

Phys. Scr.

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Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors. The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn't entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach. The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18 % and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parameters in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability. This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

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Section: Variability and Noise Analysis Of Domino Buffer Circuitsmentioning

confidence: 92%

INDIDO: A novel low-power approach for domino logic circuits

Mushtaq,

Akram,

Prasad

et al. 2024

Phys. Scr.

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Implementation of Ripple Carry Adder and Carry Save Adder using 7nm FinFET Technology

M. B.,

S. K.

2023

Wseas Transactions on Electronics

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The semiconductor industry’s continuous effort to miniaturize and be more powerful to increase the overall performance. This has led to the use of FinFET technology for packing more transistors into a smaller space and using power more efficiently compared to planner MOS technologies. Compared to the MOS technology, FinFET technology provides better advantages such as improved transistor performance, lower leakage currents, and enhanced power efficiency. The proposed work includes integrating fundamental components like the NAND gate, 2:1 MUX, and full adder (FA). These components are combined to build both Ripple Carry Adder (RCA) and Carry Save Adder (CSA). The work is carried out using 7nm FinFET technology and this research involves a thorough analysis of power consumption and propagation delay, with the implementation carried out using the Cadence Virtuoso tool. The study highlights the improved performance of 7nm FinFET technology compared to MOSFETs.

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Robustness Analysis of 3–2 Adder Compressor Designed in 7-nm FinFET Technology

Cited by 2 publications

References 16 publications

INDIDO: A novel low-power approach for domino logic circuits

INDIDO: A novel low-power approach for domino logic circuits

Implementation of Ripple Carry Adder and Carry Save Adder using 7nm FinFET Technology

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