Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

Abstract

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Simulations and Measurements of Failure Modes in SiC Cascode JFETs under Short Circuit Conditions

“…SiC Cascode JFETs are a promising device technology that combines the gate oxide reliability of silicon MOSFETs with the fast switching of SiC MOSFETs [1,2]. SiC MOSFETs have been reported to have reduced gate oxide reliability compared to silicon MOSFETs and IGBTs [3][4][5][6][7], hence, the Cascode is attractive because it avoids the problem of increased interface trap density and fixed oxide traps in SiC/SiO2 MOS interfaces. The cascode is formed by connecting a low voltage (LV) silicon MOSFET between the gate-source terminals of a High Voltage (HV) SiC JFET so that the normally ON operation of the JFET is converted into normally OFF operation (as long as the MOSFET breakdown voltage is larger than the magnitude of the JFET pinch-off voltage).…”

Stability, Reliability, and Robustness of GaN Power Devices: A Review

“…The UIS test is a widely-used method to characterize the power device surge-energy robustness. It is a JEDEC standard [175] and has been routinely used to measure the EAVA and BV AVA [176]- [178]. The UIS tests of GaN HEMTs have been reported since 2016 [179]- [184].…”

UIS performance and ruggedness of stand-alone and cascode SiC JFETs

“…Initial investigations [11] indicated a peculiar performance of SiC cascode JFETs, especially at high temperature, resulting in a reduced turn-OFF dVDS/dt and a dip in drain-source voltage during avalanche, as shown in Fig. 3, for a case temperature of 105 °C.…”

“…The SiC cascode has potential to be used in different applications, like electric vehicles [10], however, in order to accelerate its adoption, further reliability and robustness studies are required. This is important given the preliminary results in [11], which indicate an unusual performance under Unclamped Inductive Switching (UIS). These unusual results appeared at high temperatures and include reduced drain-source voltage VDS during avalanche, increased avalanche duration and reduced drain-source voltage switching rate (dVDS/dt) during the avalanche transient.…”