Robustness evaluation of finFET transistors under PVT variability

The future prospects of complementary metal oxide semiconductor (CMOS) technology are estimated to be replaced by fin-shaped field effect transistor (FinFET) owing to its strong channel control, high driving capability and ease of fabrication. This paper envisages the effects of voltage, temperature and fin variation on power dissipation and delay for static and domino logic circuits. Circuit behavior becomes unpredictable due to process, voltage and temperature (PVT) variations such as irregular power consumption and performance deviation. It also accelerates circuit deterioration and makes them ineffective. The important circuit level leakage power reduction techniques like LCNT, LECTOR and INDEP have been applied to basic gates, 3-bit carry look ahead adder (CLA) and domino logic circuits at 16[Formula: see text]nm FinFET technology. It is found that power delay product (PDP) in CLA using INDEP technique exhibits 61.48% less than conventional CLA. Leakage power reduction techniques have also been verified for the footer domino logic (FDL) circuit and performed Monte Carlo simulations for 10000 samples for reliability analysis. INDEP circuits are robust to PVT variations. The simulations have been completed using Cadence Virtuoso tool.

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Robustness evaluation of finFET transistors under PVT variability

Cited by 2 publications

References 9 publications

Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node

Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node

Performance Comparison for FinFET Nanoscale Static and Domino Logic Circuits

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