Role of Grain Boundary Sliding in Structural Integrity of Cu-Filled Through Si Via During Isothermal Annealing

Sonawane, Dipali; Kumar, Praveen

doi:10.1007/s11664-020-08476-1

Cited by 6 publications

(3 citation statements)

References 31 publications

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“…The period and critical size of the TSV-Cu structure are on the microscale for both vertical and horizontal dimensions. However, during CMP and annealing processes, the accuracy of the zdirection of Cu must be controlled at the nanolevel 5,15,16 . Cross-scale defect characterization in the zdirection of TSV-Cu structures is a significant challenge.…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, three-dimensional (3D) integrated circuit (IC) technology with the through-silicon via (TSV) has attracted significant attention because of its versatility, small size, and high performance. 3D IC is a technology that reduces the overall wire length and delay by vertically stacking multiple chips through high-density chip-to-chip interconnects [1][2][3][4][5][6][7] . TSV technology involves several processes, including etching holes in Si chips, depositing insulating/blocking/seeding layers, filling blind holes with Cu conductors, removing the backside Si and Cu overlay films via chemical-mechanical planarization (CMP) to expose Cu microcartridges, and ball bonding 8,9 .…”

Section: Introductionmentioning

confidence: 99%

“…When many defects appear during the TSV process, the detection time obtained using conventional methods is unsatisfactory 5,9 . The period and critical size of the TSV-Cu structure are on the microscale for both vertical and horizontal dimensions.…”

Section: Introductionmentioning

confidence: 99%

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Nondestructive monitoring of annealing and chemical–mechanical planarization behavior using ellipsometry and deep learning

Song

Sun

Yang

et al. 2022

Preprint

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The Cu-filling process in through-silicon via (TSV-Cu) is a key technology for chip stacking and three-dimensional vertical packaging. During this process, defects resulting from chemical–mechanical planarization (CMP) and annealing severely affect the reliability of the chips. Traditional methods of defect characterization are destructive and cumbersome. In this study, a new defect inspection method was developed using Mueller matrix spectroscopic ellipsometry. TSV-Cu with a 3-µm-diameter and 8-µm-deep Cu-filling showed three typical types of defects: over-dishing (defect-OD), protrusion (defect-P), and defect-free defects. The process window for each defect was 13 nm. First, the three typical defects caused by CMP and annealing were investigated. With single-channel deep learning and a Mueller matrix element (MME), the TSV-Cu defect types could be distinguished with an accuracy rate of 99.94%. Next, seven effective MMEs were used as seven channels in the artificial neural network to quantify the height variation in the Cu-filling in the z-direction. The accuracy rate was 98.92% after training, and the recognition accuracy reached 1 nm. The proposed approach rapidly and nondestructively evaluates the annealing bonding and CMP processes, which can improve the reliability of high-density integration.

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Section: Introductionmentioning

confidence: 99%