Role of hole fluence in gate oxide breakdown

Li, M.F.; He, Yandong; Ma, Siguang; Cho, B.-J.; Lo, K.F.; Xu, Mingzhen

doi:10.1109/55.798052

Cited by 12 publications

(2 citation statements)

References 11 publications

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“…This result has been confirmed, 360,361 and further, substrate hot hole injection experiments indicate that a critical hole fluence is needed to trigger oxide breakdown. 362,363 In Fig. 53, Q p,crit and Q BD , measured over a wide field range of 8 -14 MV/cm, are plotted.…”

Section: Hole Fluencementioning

confidence: 99%

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Green¹,

Gusev

Degraeve

et al. 2001

Journal of Applied Physics

748

345

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The outstanding properties of SiO 2 , which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO 2 interface, which forms the heart of the modern metal-oxide-semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin ͑Ͻ4 nm͒ SiO 2 and Si-ON ͑silicon oxynitride͒ gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices will be manufactured with SiO 2 and Si-ON for the foreseeable future, continued scaling of integrated circuit devices, essentially the continued adherence to Moore's law, will necessitate the introduction of an alternate gate dielectric once the SiO 2 gate dielectric thickness approaches ϳ1.2 nm. It is hoped that this article will prove useful to members of the silicon microelectronics community, newcomers to the gate dielectrics field, practitioners in allied fields, and graduate students. Parts of this article have been adapted from earlier articles by the authors ͓L.

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Section: Hole Fluencementioning

confidence: 99%

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Green¹,

Gusev

Degraeve

et al. 2001

Journal of Applied Physics

748

345

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“…It is strongly believed that the dielectric degradation process does not come directly from the electron conduction, but indirectly from the current-induced holes [7][8][9][10]37] that are generated when the electrons finally reach the anode. When an electron reaches the anode it has excessive energy and must thermalize.…”

Section: Electron and Hole Injection Into Siomentioning

confidence: 99%

Molecular model for intrinsic time-dependent dielectric breakdown in SiO₂dielectrics and the reliability implications for hyper-thin gate oxide

McPherson

Khamankar

2000

Semicond. Sci. Technol.

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SiO 2 films, at constant electric field, show a significant reduction in time-dependent dielectric breakdown (TDDB) performance when the thickness t ox is scaled below 4.0 nm. This reduction in TDDB performance is coincident with and scales with the increase in direct tunnelling (DT) leakage through these hyper-thin oxide films. Assuming that the increase in DT leakage leads to more hole injection and trapping in the SiO 2 , the enhanced dielectric degradation rate with t ox reduction can be explained on the basis of an intrinsic molecular model where hole capture serves to catalyze Si-O bond breakage.

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Oxide Reliability Issues

Degraeve¹

High Dielectric Constant Materials

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Role of hole fluence in gate oxide breakdown

Cited by 12 publications

References 11 publications

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Molecular model for intrinsic time-dependent dielectric breakdown in SiO₂dielectrics and the reliability implications for hyper-thin gate oxide

Oxide Reliability Issues

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Role of hole fluence in gate oxide breakdown

Cited by 12 publications

References 11 publications

Ultrathin (&lt;4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (&lt;4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Molecular model for intrinsic time-dependent dielectric breakdown in SiO2dielectrics and the reliability implications for hyper-thin gate oxide

Oxide Reliability Issues

Contact Info

Product

Resources

About

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Molecular model for intrinsic time-dependent dielectric breakdown in SiO₂dielectrics and the reliability implications for hyper-thin gate oxide