Role of Phonon Scattering in a Junctionless Carbon Nanotube Field-Effect Diode

Khorsand, Vahid; Yousefi, Reza; Afzalian, Amard

doi:10.1007/s11664-022-10195-8

Cited by 1 publication

(2 citation statements)

References 31 publications

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“…This advantage is attained using silicon-based technologies, which make the integration of siliconbased circuits feasible. However, other distinctive structures have been proposed in the form of FEDs based on carbon nanotube [21,22], AlGaN/GaN [47], and graphene [48] with specific applications. An AlGaN/GaN high electron mobility transistor (HEMT)-compatible lateral field-effect diode has been used to develop a zero-bias microwave power detector [47].…”

Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

“…In addition, channel pinch-off causes the drain current to be saturated. To overcome these challenges, carbon nanotube field effect transistors (CNTFETs) [8][9][10][11], FETs based on nanowire structures (NW-FETs) [12][13][14][15], thin-film transistors (TFTs) [16,17], and field effect diodes (FEDs) [18][19][20][21][22] were proposed. CNTFETs are characterized as transistors with high mobility, low power consumption, and small size.…”

Section: Introductionmentioning

confidence: 99%

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Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

GolshanBafghi,

Rezaei,

Ghafouri

et al. 2023

JCHAR

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Nanostructured solid-state devices demonstrate prominent electronic transport properties and thus represent powerful building blocks for a wide range of analog and digital integrated circuits and systems. In this study, the integration of the side-contacted field effect diode (S-FED) with the silicon nanowire concept is pursued to create a device that maintains a substantial aspect ratio while delivering suitable execution. The nanowire side-contacted FED (NW-SFED), referred to as this apparatus, exhibits the capability to achieve an exceptionally high ON/OFF current ratio of 4×10 8 , allowing for efficient switching between ON and OFF states. While the downscaling of the planar CMOS technology has faced severe constraints, this characteristic is featured as a figure of merit for the NW-SFED device. Accordingly, the device can also be used in a coordinated device-circuit co-design framework as a promising candidate to mitigate noise, delay, and energy. Herein, a quantitative evaluation of NW-SFED's performance is conducted utilizing a semiconductor drift-diffusion solver to explore how variations in channel length, device width, as well as the dimensions of the n + and p + doped regions in the source and drain, respectively, influence its operational characteristics. The impact of the channel length, spacer length and device width on NW-SFED fabrication turned out to be negligible. In contrast, the thickness of doped regions emerged as the critical parameter in the fabrication process.

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