Role of the deep parasitic bipolar device in mitigating the single event transient phenomenon

Mikami, N.; Nakauchi, T.; Oyama, Akira; Kobayashi, Hajime; Usui, Hiroki

doi:10.1109/irps.2009.5173384

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…In addition to a lack of distinction between SETs from nMOSFET and pMOSFET, there were issues with the measurement accuracy of SET pulse width [15]- [17]. SET pulse width can be modulated during propagation through logic gates since SET pulse widths are generally measured using a long logic chain [18]. This propagation-induced pulse modulation (shrinking / broadening) is caused by the difference between the rise and fall propagation times.…”

Section: Introductionmentioning

confidence: 99%

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

FURUTA,

SUGITANI,

NAKAJIMA

et al. 2024

IEICE Trans. Electron.

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Radiation-induced temporal errors become a significant issue for circuit reliability. We measured the pulse widths of radiationinduced single event transients (SETs) from pMOSFETs and nMOSFETs separately. Test results show that heavy-ion induced SET rates of nMOS-FETs were twice as high as those of pMOSFETs and that neutron-induced SETs occurred only in nMOSFETs. It was confirmed that the SET distribution from inverter chains can be estimated using the SET distribution from pMOSFETs and nMOSFETs by considering the difference in load capacitance of the measurement circuits.

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Section: Introductionmentioning

confidence: 99%

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

FURUTA,

SUGITANI,

NAKAJIMA

et al. 2024

IEICE Trans. Electron.

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show abstract

“…However, they are very weak to an SET pulse from the C-elements. On the other hand, MCU is well known as a critical issue on SRAMs, since it cannot be recovered by ECC circuits [2]. Recently, so-called tapless standard cells are widely used to control well potentials [3].…”

Section: Introductionmentioning

confidence: 99%

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles

Furuta¹,

Hamanaka²,

Kobayashi³

et al. 2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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We fabricated a 65nm LSI including flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. It consists of two FF arrays as follows. One is an array composed of redundant FFs to confirm radiation hardness of the proposed and conventional redundant FFs. The other is an array composed of conventional D-FFs to measure SEU (Single Event Upset) and MCU(Multiple Cell Upset) by the distance from tap cells.

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Parasitic bipolar effects on soft errors to prevent simultaneous flips of redundant flip-flops

Zhang

Yamamoto

Furuta³

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Role of the deep parasitic bipolar device in mitigating the single event transient phenomenon

Cited by 6 publications

References 8 publications

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles

Parasitic bipolar effects on soft errors to prevent simultaneous flips of redundant flip-flops

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