Role of wafer geometry in wafer chucking

Turner, Kevin T.; Ramkhalawon, Roshita; Sinha, Jaydeep K.

doi:10.1117/1.jmm.12.2.023007

Cited by 12 publications

(10 citation statements)

References 6 publications

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“…4, showing excellent correlation. Similar comparisons were performed for many different wafer shapes 8 with similar good correlation. For wafers having nominal warp values ≤100 μm, good agreement was observed between FE modeled IPD and the wafer shape derived PIR.…”

Section: Relationship Between Wafer Geometry Andmentioning

confidence: 84%

“…(4) defining the lateral displacement at the midsurface u 0 , we can break the top surface displacement into two pieces. The first term (−ðh∕2Þdw∕dx) can be identified as the pure bending term, 7,8 representing a pivoting about the wafer midsurface by angle ϕ. The second term, u 0 , represents the lateral displacement of the wafer midsurface.…”

Section: Relationship Between Wafer Geometry Andmentioning

confidence: 99%

“…The chucking performance depends on a combination of the chucking forces and the spatial wavelengths contained in the shape of the wafer being chucked and has been reported elsewhere. 8 But constant magnification components, i.e., simple M x and M y components of Eq. (1), will be accurately corrected by the normal scanner alignment process.…”

Section: Relationship Between Wafer Geometry Andmentioning

confidence: 99%

See 2 more Smart Citations

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Brunner

Menon

Wong

et al. 2013

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

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Section: Relationship Between Wafer Geometry Andmentioning

confidence: 84%

Section: Relationship Between Wafer Geometry Andmentioning

confidence: 99%

Section: Relationship Between Wafer Geometry Andmentioning

confidence: 99%

See 1 more Smart Citation

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Brunner

Menon

Wong

et al. 2013

J. Micro/Nanolith. MEMS MOEMS

Self Cite

View full text Add to dashboard Cite

show abstract

“…Low frequency wafer shape can be eliminated during chucking, whereas higher order wafer shape might contribute to overlay residuals and can cause wafer non-chuckability resulting in defocus. Impact of wafer shape on overlay has been studied through theoretical, finite element models and validated through experimental results (2). Flatness is a thickness based parameter and is primarily quantified using metrics such as site front surface least square reference range (SFQR) and site back surface ideal reference range (SBIR).…”

Section: Introductionmentioning

confidence: 99%

Lithographic Significance of Wafer Back Surface Nanotopography

Veeraraghavan

Sinha

2010

ECS Trans.

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Wafer topography plays a critical role in the performance of lithography at smaller nodes. The contribution of low to medium spatial frequency components of wafer topography to overlay error is currently a topic of interest within the lithography community, especially as double patterning techniques have reduced overlay error budgets by a factor of two. Nanotopography, comprised of the higher spatial frequency components of wafer topography can contribute to non-correctable errors (NCE) for the scanner. In this paper we use finite element analysis to investigate the transfer of back-surface nanotopography to the front surface as the wafer is chucked either on a pin chuck or a flat vacuum chuck. The results are found to be lithographically significant, suggesting that fabs may benefit from measuring back-surface nanotopography, and developing appropriate specs for incoming wafers.

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“…In this process, both the wafer shape and the overlay error (in the x and y directions) can be represented as images as shown in Figure 1. Prediction of the overlay error across a wafer based on the wafer shape can be fed forward to exposure tools for specific corrections (Turner et al, 2013). In order to predict the overlay error based on the wafer shape deformation, an image-on-image statistical model is required to capture the correlation between the wafer overlay and shape.…”

Section: Introductionmentioning

confidence: 99%

A novel approach for fusion of heterogeneous sources of data

Gahrooei,

Yan,

Paynabar

et al. 2018

Preprint

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With advancements in sensor technology, heterogeneous sets of data such as those containing scalars, waveform signals, images, and even structured point clouds, are becoming increasingly popular. Developing statistical models based on such heterogeneous sets of data to represent the behavior of an underlying system can be used in the monitoring, control, and optimization of the system. Unfortunately, available methods only focus on the scalar and curve data and do not provide a general framework for integrating different sources of data to construct a model. This paper addresses the problem of estimating a process output, measured by a scalar, curve, image, or structured point cloud by a set of heterogeneous process variables such as scalar process setting, sensor readings, and images. We introduce a general multiple tensoron-tensor regression (MTOT) approach in which each set of input data (predictor) and output measurements are represented by tensors. We formulate a linear regression model between the input and output tensors and estimate the parameters by minimizing a least square loss function. In order to avoid overfitting and reduce the number of parameters to be estimated, we decompose the model parameters using several bases that span the input and output spaces.Next, we learn the bases and their spanning coefficients when minimizing the loss function using a block coordinate descent algorithm combined with an alternating least square (ALS) algorithm. We show that such a minimization has a closed-form solution in each iteration and can be computed very efficiently. Through several simulation and case studies, we evaluate the performance of the proposed method. The results reveal the advantage of the proposed method over some benchmarks in the literature in terms of the mean square prediction error.

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Role of wafer geometry in wafer chucking

Cited by 12 publications

References 6 publications

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Lithographic Significance of Wafer Back Surface Nanotopography

A novel approach for fusion of heterogeneous sources of data

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