Roofline-aware DVFS for GPUs

Nugteren, Cedric; Braak, Gert-Jan van den; Corporaal, Henk

doi:10.1145/2553062.2553067

Cited by 11 publications

(12 citation statements)

References 11 publications

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“…Jia et al [5] and Nugteren et al [6] proposed the GPU roofline and DVFS algorithm on the GPU. For easy construction of the roofline model, Steinmann [7] developed and distributed a tool that automatically records the kernel operation intensity on a x86 architecture.…”

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confidence: 99%

A roofline model based on working set size for embedded systems

Cho

Yun

Jeon

2014

IEICE Electron. Express

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A "roofline model" is a system performance and optimization guide for programmers and system engineers to apply in the design of future architectures. We review a conventional roofline model and propose a working set size (WSS)-based roofline model. Because of the recent increase in the performance of embedded systems, we investigated embedded systems based on an ARM architecture. Our proposed scheme presents practical guidelines for a multi-core architecture when the program uses a small WSS.

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confidence: 99%

A roofline model based on working set size for embedded systems

Cho

Yun

Jeon

2014

IEICE Electron. Express

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“…The commonly used approach is to either fix the DDR frequency at the highest level, or to map unique pairs of CPU/GPU and DDR frequencies, selected statically (i.e, at design time) to a DVFS level (this is the approach QoS-aware DVFS utilizes). To the best of our knowledge, there are only two previous studies that considered DDR frequency scaling for GPGPU applications [66,68]. Their solutions do not fully consider the interrelationship between the GPU and DDR frequencies for maximum efficiency; also their work is not directly applicable to 3D graphics workloads.…”

Section: Discussionmentioning

confidence: 99%

“…It is notable that variations of performance and/or power models have been used in CPU DVFS techniques before [62,64,13]. Performance [66,68] and power [67] models have also been developed for GPGPU power management Recently, Pathania et al described statistical models for mobile GPU gaming workloads [16]. These existing solutions do not sufficiently satisfy one or more of the following requirements: (1) Low-latency, fine-grained, individual frame-level models for both performance and energy prediction that are required for graphics rendering workloads with soft-realtime deadlines.…”

Section: Discussionmentioning

confidence: 99%

“…[68]. Besides compute-to-memory intensity factor similar to [66], they used 7 other performance counters to characterize workload phases. Using regression analysis, they derived a sensitivity model for core frequency and the number of cores, as well as memory bandwidth.…”

Section: Dynamic Voltage and Frequency Scalingmentioning

confidence: 99%

“…Nugteren et al proposed a GPGPU DVFS solution with two frequency domains, i) GPU and ii) main memory[66]. They identify if a compute kernel is compute or memory-bound using asimple two-part piecewise linear model based on ops/byte.…”

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Dynamic voltage and frequency scaling for 3D graphics applications on the state-of-the-art mobile GPUs

Farazmand¹

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AHB Advanced High-performance Bus. System bus definition within the AMBA 2.0 specification.Defines a high-performance bus including pipelined access, bursts, split, and retry operations. DVFS Dynamic Voltage and Frequency Scaling. Group of algorithms that change voltage and frequency at runtime according to workload to make a trade-off between performance and energy consumption DDR Double Data Rate memory. DDR refers to a specific type of dynamic memory technology, which is synonymous with the dynamic memory used as the global (volatile) memory in computing elements. DOU Days Of Use. For a mobile device, the length of the time from a full battery (re)charge to when the battery dies and requires another recharge. It is often used by different vendors with a predefined set of dashboard tests they use to define their target energy consumption requirements. These requirements are used to drive the design, measure the success of the design, and compare competing designs and platforms. CPU Central Processing Unit. GPU Graphics Processing Unit. GPGPU General-Purpose computing on GPU. There are a number of general-purpose (nongraphics) applications that can benefit significantly from the parallelism offered by graphics processors in terms of performance. GPGPU refers to the concept of running general-purpose (nongraphics) applications on GPUs. OPP Operating Performance Point. A unique permutation of all the frequency domains controlled by DCVS. In this thesis, it refers to the (GPU,DDR) frequency pair. IC Integrated Circuit. PMIC Power Management Interface Controller. The component within of a digital electronic chipset that controls the power distribution and protects the circuit from permanent damage, or data corruption due to voltage droop. It is also in charge of optimizing power distribution to increase battery efficiency. IoE Internet of Everything. IoT Internet of Things. SoC System on a Chip. Refers to the integration of multiple different electronic elements including processors and memories on a single chip in a single fabrication process API Application Programming Interface. A set of well-defined functions that specify the interface of a library with other software components. External components and interact with and use the library by calling its API functions. API only specifies the format of the functions and their behavior as seen by outside entity. It does not expose internal implementation of those behaviors.ix UMD User Mode Driver. A device driver that runs in user-mode in the operating system and acts as the interface between an application and a device driver. IO Input/Output. ADB Android Debug Bridge. Set of command line tools available for the Android operating system, which are used for debugging android operating system and applications. ADB is also used for automation tasks such as starting and stopping applications.

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Evaluation of DVFS techniques on modern HPC processors and accelerators for energy‐aware applications

Calore

Gabbana

Schifano

et al. 2017

Concurrency and Computation

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SUMMARYEnergy efficiency is becoming increasingly important for computing systems, in particular for large scale HPC facilities. In this work we evaluate, from an user perspective, the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques, assisted by the power and energy monitoring capabilities of modern processors in order to tune applications for energy efficiency. We run selected kernels and a full HPC application on two high-end processors widely used in the HPC context, namely an NVIDIA K80 GPU and an Intel Haswell CPU. We evaluate the available trade-offs between energy-to-solution and time-to-solution, attempting a function-by-function frequency tuning. We finally estimate the benefits obtainable running the full code on a HPC multi-GPU node, with respect to default clock frequency governors. We instrument our code to accurately monitor power consumption and execution time without the need of any additional hardware, and we enable it to change CPUs and GPUs clock frequencies while running. We analyze our results on the different architectures using a simple energy-performance model, and derive a number of energy saving strategies which can be easily adopted on recent high-end HPC systems for generic applications.

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Roofline-aware DVFS for GPUs

Cited by 11 publications

References 11 publications

A roofline model based on working set size for embedded systems

A roofline model based on working set size for embedded systems

Dynamic voltage and frequency scaling for 3D graphics applications on the state-of-the-art mobile GPUs

Evaluation of DVFS techniques on modern HPC processors and accelerators for energy‐aware applications

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