Room temperature Coulomb blockade effects in Au nanocluster/pentacene single electron transistors

Zheng, Haisheng; Asbahi, Mohamed; Mukherjee, Somik; Mathai, Cherian J.; Gangopadhyay, Keshab; Yang, Joel K. W.; Gangopadhyay, Shubhra

doi:10.1088/0957-4484/26/35/355204

Cited by 27 publications

(28 citation statements)

References 34 publications

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“…To calculate the gate bias required to charge the embedded Pt layer, the NP size and areal density dependent charging energy needs to be taken into consideration. Charging an NP with electrons are often associated with two kinds of energies: Coulomb charging energy (CCE) and quantum confinement energy (QCE), where the CCE arises from the self‐capacitance of the NP and the quantum confinement is linked to the spatial confinement of electrons . The calculated values of the bias required to program these NPs ( V b ), QCE and CCE for different NP sizes employed in this study are listed in Table 1 .…”

Section: Resultsmentioning

confidence: 99%

Influence of Pt Nanoparticle Induced Defects and Surface Coverage in Determining Asymmetric Programming/Erasing Signatures for Nanocrystal Embedded Nonvolatile Memory Applications

Mukherjee

Zheng

Gangopadhyay

et al. 2016

Adv Materials Inter

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semiconductor counterpart due to large density of states, 3D electric fi eld enhancement, and selectable work function. [ 1,[3][4][5][6] Considerable work has focused on the controlled synthesis of metallic NCs for use in NVM devices. Although a wide range of metal nanocrystals have been utilized to realize functioning NVM, the lack of control over the embedded NP size, interparticle distance (areal density) makes it diffi cult to investigate the electron/hole charging characteristics as a function of embedded nanocrystal properties. To achieve the desired metal NP embedded layer for NVM applications, a CMOS compatible tilted target sputtering (TTS) technique has been previously developed [ 7 ] and is employed in this study to achieve nanoparticles (NPs) with controllable sizes, areal densities, and narrow size distributions. Using the TTS technique, the average size of the NPs can be effectively controlled by varying the deposition time with constant pressure, power, and gas fl ow rate at room temperature. [ 7,8 ] This technique has been shown to produce uniformly distributed spherical Pt NPs with mean diameters between 0.5 and 2 nm, and for certain process parameters, high areal densities as large as 10 13 cm −2 . Although embedding these Pt NPs in Al 2 O 3 has resulted in NVM devices displaying large memory windows and excellent retention characteristics, [ 5,6 ] a systematic study analyzing the effect of the deposited Pt NP size, areal density, and surface coverage on the quality/magnitude of introduced trap within the surrounding dielectric has not been reported yet. In this study, the infl uence of TTS sputtered Pt NP size, areal density, and surface coverage on the charging/discharging characteristics of Pt NP embedded NVM MOS capacitors has been explored. Three different Pt Np size domains (0.7, 0.9, and 1.6 nm) and two different areal density domains (≈5 × 10 12 cm −2 and ≈10 × 10 12 cm −2 ) were explored under the realms of this study utilizing variable frequency and scan rate dependent capacitance-voltage ( C -V ) and conductance-voltage ( G -V ) measurements. The observed experimental anomalous features within the C -V and G -V signatures have been correlated to the infl uence of different types Metal nanocrystal embedded nonvolatile memory (NVM) devices have attracted signifi cant attention over the past two decades as promising alternatives to conventional fl oating gate memory devices. This study explores the applicability of sub-2 nm Pt nanoparticle (NP) embedded in ALD Al 2 O 3 as charge storage nodes in Si-based NVM devices. The infl uence of Pt NPinduced border traps within Al 2 O 3 near the Si surface and their surface coverage dependent pinning of Pt NP work function are explored as part of this study. The pinning of the nanocrystal memories induced by a high density of dangling bonds near the Pt NP/Al 2 O 3 interface skews the expected charging/ discharging characteristics with electron programming favored over holes. The degree of this pinning has been probed utilizing C -V measurements and...

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Section: Resultsmentioning

confidence: 99%

Influence of Pt Nanoparticle Induced Defects and Surface Coverage in Determining Asymmetric Programming/Erasing Signatures for Nanocrystal Embedded Nonvolatile Memory Applications

Mukherjee

Zheng

Gangopadhyay

et al. 2016

Adv Materials Inter

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“…The application of large temperature gradients is an issue in two dimensional electron gases, but some advances in quantum dots embedded into nanowires has been recently achieved 36 . Also, recent room temperature detection of Coulomb blockade in nanoparticles 75 , and quantum inteference in molecular junctions [76][77][78][79][80] are promising advances toward the application of the effects discussed here in thermal devices.…”

Section: Discussionmentioning

confidence: 99%

Thermal rectification with interacting electronic channels: Exploiting degeneracy, quantum superpositions, and interference

Marcos-Vicioso¹,

López-Jurado²,

Ruiz-García³

et al. 2018

Phys. Rev. B

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This paper explores different mechanisms that induce thermal rectification in the nanoscale. The presence of interacting energy channels combined with simple asymmetries is sufficient for promoting the desired behavior. We use simple quantum dot configurations, identifying the basic properties that enhance rectification for each case: the size of a quantum dot state space (which suggests the use of scaled up systems with many interacting channels), tunneling asymmetries due to coherent tunneling in a double quantum dot, or quantum interference in a triangular triple quantum dot. An efficient and tunable thermal diode is proposed using a channel capacitively coupled to a mesoscopic switch.

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“…This process is prevented by coulomb blockade phenomena. It affects on the energy levels of the island as well as source and drain electrodes [5,6]. If energy level of the electron in the island is between energy levels of drain and source (transfer window), the electron can tunnel and current flows [7].…”

Section: -Introductionmentioning

confidence: 99%

Investigating the electrical characteristics of a single electron transistor utilizing graphene nanoribbon as the island

Khademhosseini

Dideban

Ahmadi

et al. 2019

J Mater Sci: Mater Electron

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Single electron transistor (SET) is a fast device with promising features in nanotechnology. Its operation speed depends on the island material, so a carbon based material such as graphene nanoribbon (GNR) can be a suitable candidate for using in SET island. The GNR band gap which depends on its width, has a direct impact on the coulomb blockade (CB) and SET current. In this research, current-voltage characteristic for the SET utilizing GNR in its island is modelled. The comparison study shows the impact of GNR width and length on the SET current. Furthermore SET quantum capacitance is modeled and effect of GNR width and temperature on the quantum capacitance are investigated.

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Room temperature Coulomb blockade effects in Au nanocluster/pentacene single electron transistors

Cited by 27 publications

References 34 publications

Influence of Pt Nanoparticle Induced Defects and Surface Coverage in Determining Asymmetric Programming/Erasing Signatures for Nanocrystal Embedded Nonvolatile Memory Applications

Influence of Pt Nanoparticle Induced Defects and Surface Coverage in Determining Asymmetric Programming/Erasing Signatures for Nanocrystal Embedded Nonvolatile Memory Applications

Thermal rectification with interacting electronic channels: Exploiting degeneracy, quantum superpositions, and interference

Investigating the electrical characteristics of a single electron transistor utilizing graphene nanoribbon as the island

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