Room-temperature-deposited dielectrics and superconductors for integrated photonics

Abstract

We present an approach to fabrication and packaging of integrated photonic devices that utilizes waveguide and detector layers deposited at near-ambient temperature. All lithography is performed with a 365 nm i-line stepper, facilitating low cost and high scalability. We have shown low-loss SiN waveguides, high-Q ring resonators, critically coupled ring resonators, 50/50 beam splitters, Mach-Zehnder interferometers (MZIs) and a process-agnostic fiber packaging scheme. We have further explored the utility of this process for applications in nonlinear optics and quantum photonics. We demonstrate spectral tailoring and octave-spanning supercontinuum generation as well as the integration of superconducting nanowire single photon detectors with MZIs and channel-dropping filters. The packaging approach is suitable for operation up to 160 • C as well as below 1 K. The process is well suited for augmentation of existing foundry capabilities or as a stand-alone process.

Superconducting Optoelectronic Circuits for Neuromorphic Computing

“…Such detectors have low signal-to-noise ratio, requiring operation with significantly higher optical powers than if superconducting detectors are employed. While it may be possible to develop neuromorphic technology based on many of these detectors, we have chosen for this article to focus on superconducting nanowire single photon detectors (SNSPDs) due to the high efficiencies (> 90%) [39] at wavelengths below the Si bandgap, simple on-chip waveguide integration [40][41][42][43][44][45][46], compact size, and speed. While operation at cryogenic temperatures imparts a fixed energy cost, the energy cost per operation is significantly decreased by allowing integration with superconducting electronics.…”

“…6(a). In this model, we assume the photons are incident upon a length of out-and-back nanowire [40][41][42][43][44][45][46] with 100 µm attenuation length, and it is assumed that two photons absorbed at the same location along the nanowire gives rise to the same resistance as a single photon absorbed at that location. For this reason, the nanowire resistance levels off as a function of number of absorbed pho-tons.…”

“…III A. Another option would be to implement the light sources in the III-V material, and then couple to lowtemperature deposited materials with low-loss waveguides [46,56] such as a-Si or SiN. A III-V platform has the advantage of high efficiency light sources, but massive scaling on III-V substrates has historically been more difficult and expensive than on Si substrates.…”

“…To achieve this level of massive interconnectivity, we propose the use of multi-layer photonics. Recent work has demonstrated the utility of low-temperature-deposited dielectrics [46,96] and superconductors [46] for scalable integrated photonics. For future massive scaling we propose the use of waveguide routing networks and dendritic arbors spanning several-and possibly up to tens-of photonic and superconducting layers.…”

“…Meaning To properly understand the behavior of the SNSPD receivers, we must analyze the optical absorption and statistical behavior of waveguide-integrated SNSPDs [40][41][42][43][44][45][46]. We first calculate the attenuation of light as a function of propagation length for 200 nm thick waveguides (t wg ) in the asymptotic slab regime.…”