Routability-constrained multi-bit flip-flop construction for clock power reduction

Crosstalk-aware multi-bit flip-flop generation for power optimization

“…The first experiment compares our improved algorithms in this work with our preliminary version [1]. The second experiment compares our approach with the approaches in [11,13,17], which do not consider the crosstalk constraint, and the last one compares ours with [19], which considers similar objectives and constraints toward the routing problem.…”

“…According to [11][12][13]17,19], the delay of a net can be modelled with respect to the corresponding wirelength. The wire length of a net, W n i , must be less than or equal to the maximum allowable wire length of the net, W n i ;max , which can be estimated based on the timing model [29].…”

“…To minimize the power consumption of the clock network, many techniques had been proposed, such as buffer sizing [4,5], clock gating [6,7], register clustering [8,9] and banking [10], and replacing 1-bit flip-flops with multi-bit flip-flops (MBFFs) [11][12][13][14][15][16][17][18][19]. Recent studies have shown the effectiveness of applying MBFFs in saving both power and area [11][12][13]16,18,19].…”

“…Recent studies have shown the effectiveness of applying MBFFs in saving both power and area [11][12][13]16,18,19]. …”

“…When considering design for testability (DFT) with MBFFs, the required routing resource utilization for a scan chain will be greatly reduced. [11][12][13][17][18][19][20][21] formulated the problem of replacing 1-bit flip-flops with MBFFs by minimizing flip-flop power consumption or the number of clock sinks while satisfying both timing and placement density constraints. Some of them additionally considered wirelength minimization [11][12][13]17], routability [18,19], and clock latency [20].…”