Routability-driven flip-flop merging process for clock power reduction

Chen, Zhiwei; Yan, Jin-Tai

doi:10.1109/iccd.2010.5647784

Cited by 19 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Adjustable delay buffers were inserted in interconnections to reduce the effect of this clock skew in the timing of the IC [18]. A legalization-based placement algorithm was also proposed [19,20] for an accurate timing analysis. In [15], MBFFs were used during the placement stage for the reduction in power and clock skew.…”

Section: Related Workmentioning

confidence: 99%

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Srinath¹,

Verma

Barnawi

et al. 2021

Electronics

View full text Add to dashboard Cite

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

show abstract

Section: Related Workmentioning

confidence: 99%

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Srinath¹,

Verma

Barnawi

et al. 2021

Electronics

View full text Add to dashboard Cite

show abstract

“…With timing analysis, we could obtain timing slack between input (output) pins and FF. By transforming the timing slack into equivalent metal wirelength using Elmore delay model [4], we can find the timing-violation-free distance (TVFD) between FF and input (output) pins. Taken the input and output TVFDs into account, each FF can find a feasible region for movement without violating timing, which we label as timing-violation-free region (TVFR) in Figure 2.…”

Section: Post-placement Mbff Problem Formulation and Previous Solutionsmentioning

confidence: 99%

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging

Luo

et al. 2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

View full text Add to dashboard Cite

Circuit clustering is usually done through discrete optimizations, with the purpose of circuit size reduction or designspecific cluster formation. Specifically, we are interested in the multi-bit flip-flop (MBFF) design technique for clock power reduction, where all previous works rely on discrete clustering optimizations. For example, INTEGRA was the only existing post-placement MBFF clustering optimizer with a sub-quadratic time complexity. However, it degrades the wirelength severely, especially for realistic designs, which may cancel out the benefits of MBFF clustering. In this paper we enable the formulation of an analytical clustering score in nonlinear programming, where the wirelength objective can be seamlessly integrated. It has sub-quadratic time complexity, reduces the clock power by about 20% as the state-of-the-art techniques, and further reduces the wirelength by about 25%. In addition, the proposed method is promising to be integrated in an in-placement MBFF clustering solver and be applied in other problems which require formulating the clustering score in the objective function.

show abstract

An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction

Gulati

Prakash

Darak

2017

Communications in Computer and Information Science

View full text Add to dashboard Cite

Routability-driven flip-flop merging process for clock power reduction

Cited by 19 publications

References 4 publications

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging

An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction

Contact Info

Product

Resources

About