Routability-driven repeater block planning for interconnect-centric floorplanning

Sarkar, P.; Koh, Cheng-Kok

doi:10.1109/43.920700

Cited by 49 publications

(87 citation statements)

References 22 publications

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“…Therefore, there is only 34 nets violate the constraints because of the failure of buffer insertion. While the best result in [3] is that 368 nets meet their [3] because that those methods are based on fix-die placement, while the floorplanning should be optimized to meet the given timing constraints in our algorithm. Even though, we can see some improvement in the results because our algorithm can give a more feasible floorplan structure for buffer insertion.…”

Section: Methodsmentioning

confidence: 99%

“…The feasible region for a buffer 'b' is the maximum region where 'b' can be located such that by inserting buffer 'b' into any location in that region, the delay constraint can be satisfied. Sarkar et al [3] gives the notion of independent feasible regions(IFR) and the IFRs of buffers belonging to the same net do not overlap each other. Here we use the concept of IFR so that the feasible regions of different buffers on a net can be computed independently.…”

Section: Computation Of Possible Buffer Insertion Sites 31 Independementioning

confidence: 99%

“…Cong [1] define the term "feasible region" (FR) of a net, that is, the largest polygon in which a buffer can be inserted such that the timing constraint can be satisfied. Sarkar [3] added the notion of independence into feasible regions so that the feasible regions of different buffers on a net can be computed independently. These two papers give the basic idea of Feasible Region, based on which they proposed the buffer planning algorithms.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An integrated floorplanning with an efficient buffer planning algorithm

Hong

Dong

et al. 2003

Proceedings of the 2003 International Symposium on Physical Design

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Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate the buffer planning with the floorplanning process. In this paper, we give an efficient buffer planning algorithm with linear complexity by computing all the feasible buffer insertion sites in a 2-step method. By partitioning all the dead spaces into blocks while doing the packing, the buffer allocation can be handled as an integral part in the floorplanning process. Our method is based on a simulated annealing approach which is divided into two phases: timing optimization phase and buffer insertion phase. Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better time performance and chip area.

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Section: Methodsmentioning

confidence: 99%

Section: Computation Of Possible Buffer Insertion Sites 31 Independementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An integrated floorplanning with an efficient buffer planning algorithm

Hong

Dong

et al. 2003

Proceedings of the 2003 International Symposium on Physical Design

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“…On one hand, designs with hundreds of million transistors are already in production, IP modules are widely reused, and a large number of buffer blocks are used for delay optimization as well as noise reduction in very deep-submicron interconnect-driven floorplanning [1, 7,11,13,21], which all drive the need of a tool to handle large-scale building modules. On the other hand, the highly competitive IC market requires faster design convergence, faster incremental design turnaround, and better silicon area utilization.…”

Section: Introductionmentioning

confidence: 99%

Multilevel floorplanning/placement for large-scale modules using B*-trees

Lee¹,

Chang

Hsu

et al. 2003

Proceedings of the 40th Annual Design Automation Conference

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We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, MB*-tree scales very well as the circuit size increases.

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“…Until recently, all previous congestion models in literature divide the whole chip area into tiles [2,3,4,5,6]. The number of wires crossing a tile boundary is estimated and is used as a measure of congestion.…”

Section: Previous Workmentioning

confidence: 99%

Accurate and eff icient flow based congestion estimation in floorplanning

Shen¹,

Chu²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Congestion has been a topic of great importance in the floorplanning of deep-submicron 0design. In this paper, we design an accurate and efficient congestion estimation model by performing global routing. We interpret the global routing problem as a flow problem of several commodities and relax the integral flow constraints. The objective of resulting fractional flow problem is to minimize the maximum congestion over all edges in the inner dual graph [13]. The underlying routing graph for each commodity is derived by assigning directions to the inner dual graph edges. We design an efficient two-phase algorithm to solve this fractional flow problem. The first phase is denoted as Incoming Flow Balancing (IFB) by which a good initial solution is derived. The second phase is called Stepwise Flow Refinement (SFR) by which the maximum congestion of the solution in first phase is iteratively reduced to its optimal value. In addition, a valid global routing solution can be obtained by applying a simple rounding procedure on the fractional flow solution. The maximum congestion after rounding is only increased by 2.82% on average according to our experimental results, which justifies the use of fractional flow to estimate the routing congestion. Finally, we demonstrate our model by integrating it into a simulated annealing (SA) based floorplanner, where we use the maximum congestion as part of the cost of SA. The experimental results show that, on average, our congestion-driven floorplanner can generate a much less congested floorplan (-36.44%) with a slight sacrifice in area (+1.30%) and wirelength (+2.64%). The runtime of the whole SA process is only increased moderately (+270%).

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Routability-driven repeater block planning for interconnect-centric floorplanning

Cited by 49 publications

References 22 publications

An integrated floorplanning with an efficient buffer planning algorithm

An integrated floorplanning with an efficient buffer planning algorithm

Multilevel floorplanning/placement for large-scale modules using B*-trees

Accurate and eff icient flow based congestion estimation in floorplanning

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