Run-Time Cache-Partition Controller for Multi-Core Systems

Danielsson, Jakob; Jägemar, Marcus; Behnam, Moris; Seceleanu, Tiberiu; Sjödin, Mikael

doi:10.1109/iecon.2019.8926758

Cited by 6 publications

(2 citation statements)

References 13 publications

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“…In 2019, Danielsson et al [110] proposed a run-time cache partition controller that optimizes the cache partitioning approach proposed by Palloc [65] by obtaining more efficient partitions using correlation-based decisions. To create efficient partitions, it focuses on LLC-bound workloads.…”

Section: ) Proposal Focused On Achieving a Better Performancementioning

confidence: 99%

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.INDEX TERMS Real-time systems, architecture, multicore, timing analysis, schedulability analysis, WCET, co-runner interference.

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Section: ) Proposal Focused On Achieving a Better Performancementioning

confidence: 99%

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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“…Implementing cache partitioning methods is one potential solution to the issue of shared resource overload. These strategies divide up the available cache lines across different applications [7] . Our proposal is a framework for heterogeneous-aware partitioning cache replacement policies (HAPC), which will lead to the AMP system operating at peak efficiency.…”

Section: Introductionmentioning

confidence: 99%

Examining partitioned caches performance in heterogeneous multi-core processors

Yenugula

2022

Int. J. Commun. Inf. Technol.

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The last-level cache (LLC) is shared by many distinct kinds of cores in asymmetric multi-core systems. There is greater rivalry in the LLC since different core types have different memory access needs. Our new technique for replacing the split cache, HAPC, takes heterogeneity into account. To improve coreto-core interference, this method uses cache partitioning. In multithreaded applications, it guides the replacement strategy by monitoring the shared reuse state of every cache block inside the partition during runtime. This ensures that cache blocks shared among different cores are maintained. For huge cores to make more efficient LLC visits, cache replacement algorithms generally modify the leftover state while preserving cache blocks needed by them. This approach takes into consideration the fact that heterogeneous cores have different memory accesses to LLC. In comparison to the state-of-the-art cache substitute's algorithms, LRU and SRCP, HAPC can greatly enhance the performance of large cores when running multithreaded applications, with almost no impact on small cores, leading to an overall improvement in system performance.

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