2005 International Symposium on System-on-Chip 2005
DOI: 10.1109/issoc.2005.1595649
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Run-time Mapping of Applications to a Heterogeneous SoC

Abstract: Abstract-This paper presents an iterative hierarchical approach to map an application to a parallel heterogeneous SoC architecture at run-time. The application is modeled as a set of communicating processes. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service. This approach is flexible, scalable and the performance looks promising.

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Cited by 37 publications
(29 citation statements)
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“…Preliminary experiments [23] were promising with respect to the feasibility of run-time spatial mapping in general. Our implementation (see Sect.…”
Section: Necessity and Advantagesmentioning
confidence: 99%
“…Preliminary experiments [23] were promising with respect to the feasibility of run-time spatial mapping in general. Our implementation (see Sect.…”
Section: Necessity and Advantagesmentioning
confidence: 99%
“…The first loop (lines 4-9) analyzes all clusters that have available resources to map the application, selecting the one with the smallest accumulated energy. If there are no clusters with available resources to map the application, a cluster with the smallest accumulated energy is selected, regardless the number of available resources (lines [11][12][13][14][15][16]. Note that the application is mapped in the MPSoC iff the system has available resources for the application.…”
Section: Cluster Selectionmentioning
confidence: 99%
“…The available SP in the list with the smallest TE is selected (lines 8-13). If no SP can be selected, the bounding box is increased by one hop (lines [14][15][16]. This process continues up to find an SP or to visit all SPs of the cluster.…”
Section: Non-initial Task Mappingmentioning
confidence: 99%
“…To reduce the energy consumption, each process is mapped on the PE that can execute it most efficiently. This so called spatial mapping of processes is performed at run-time by the spatial mapping tool [5]. Run-time mapping offers a number of advantages over design-time mapping.…”
Section: Run-time Mappingmentioning
confidence: 99%
“…In our case, the Montium tiles have single port memories, so we can derive the throughput of the sample application by combining three inequalities (5).…”
Section: B Predicting the Throughput Of A Single Processmentioning
confidence: 99%