Run-time power-down strategies for real-time SDRAM memory controllers

Chandrasekar, Karthik; Åkesson, Benny; Goossens, Kees

doi:10.1145/2228360.2228538

Cited by 10 publications

(4 citation statements)

References 14 publications

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“…In [8], compiler techniques are presented, which exploit the DRAM powerdown states. Chandrasekar et al [5] present two power-down strategies that reduce memory energy consumption while still preserving the guaranteed bandwidth provided by real-time memory controllers. Furthermore, they present an algorithm to select the most energy-efficient power-down mode at run-time.…”

Section: Dram Power-downmentioning

confidence: 99%

Integrating DRAM power-down modes in gem5 and quantifying their impact

Jagtap

Jung

Elsasser

et al. 2017

Proceedings of the International Symposium on Memory Systems

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Across applications, DRAM is a significant contributor to the overall system power, with the DRAM access energy per bit up to three orders of magnitude higher compared to on-chip memory accesses. To improve the power efficiency, DRAM technology incorporates multiple power-down modes, each with different trade-offs between achievable power savings and performance impact due to entry and exit delay requirements. Accurate modeling of these low power modes and entry and exit control is crucial to analyze the tradeoffs across controller configurations and workloads with varied memory access characteristics. To address this, we integrate the power-down modes into the DRAM controller model in the opensource simulator gem5. This is the first publicly available full-system simulator with DRAM power-down modes, providing the research community a tool for DRAM power analysis for a breadth of use cases. We validate the power-down functionality with sweep tests, which trigger defined memory access characteristics. We further evaluate the model with real HPC workloads, illustrating the value of integrating low power functionality into a full system simulator

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Section: Dram Power-downmentioning

confidence: 99%

Integrating DRAM power-down modes in gem5 and quantifying their impact

Jagtap

Jung

Elsasser

et al. 2017

Proceedings of the International Symposium on Memory Systems

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“…It can be scheduled after a read or write pattern. Finally, the idle time of the controller can be discretized explicitly into 6) idle or powerdown patterns [18]. A collection of these six patterns is called a pattern set.…”

Section: Memory Patternsmentioning

confidence: 99%

“…The ADDACTANDRW function schedules an activate command using ADDACT before the first burst to a bank (lines [17][18]. Additionally, it schedules the read/write commands as soon as possible (lines 16,19).…”

Section: Pattern Generationmentioning

confidence: 99%

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Goossens

Chandrasekar

Åkesson

et al. 2016

IEEE Trans. Comput.

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Abstract-Real-time safety-critical systems should provide hard bounds on an applications' performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers' performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.

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“…In our third experiment, we compare the energy estimates reported by the two power models for different workloads on all four channels of the memory. For this analysis, we employed the four memory traces obtained using the four MediaBench applications and employed either the power-down mode or the self-refresh mode for the idle periods [32] in all of them. We then increased the trace player frequency in steps, thereby varying the rate of traffic injection to the memory.…”

Section: Energy Comparison For Different Memory Loadsmentioning

confidence: 99%

System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs

Chandrasekar

Weis

Åkesson

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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JEDEC recently introduced its new standard for 3Dstacked Wide I/O DRAM memories, which defines their architecture, design, features and timing behavior. With improved performance/power trade-offs over previous generation DRAMs, Wide I/O DRAMs provide an extremely energy-efficient green memory solution required for next-generation embedded and highperformance computing systems. With both industry and academia pushing to evaluate and employ these highly anticipated memories, there is an urgent need for an accurate power model targeting Wide I/O DRAMs that enables their efficient integration and energy management in DRAM stacked SoC architectures.In this paper, we present the first system-level power model of 3D-stacked Wide I/O DRAM memories that is almost as accurate as detailed circuit-level power models of 3D-DRAMs. To verify its accuracy, we experimentally compare its power and energy estimates for different memory workloads and operations against those of a circuit-level 3D-DRAM power model and show less than 2% difference between the two sets of estimates.

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Run-time power-down strategies for real-time SDRAM memory controllers

Cited by 10 publications

References 14 publications

Integrating DRAM power-down modes in gem5 and quantifying their impact

Integrating DRAM power-down modes in gem5 and quantifying their impact

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs

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