Run-time self-reconfigurable 2D convolver for adaptive image processing

Fons, Francesc; Fons, Mariano; Cantó, Enrique

doi:10.1016/j.mejo.2010.08.008

Cited by 19 publications

(6 citation statements)

References 5 publications

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“…In the other methods, different pipelining techniques, are exploited to increase the throughput of the proposed design. For example in [15,[19][20] the convolution is expressed as the sum-of-products among the image's pixels and the coefficients of the kernel while the ordinary pipelined convolver exploits separate pipeline stages for buffering, multiplication, and adder modules. Also, the proposed design works with high clock frequency, but it is at the expense of a huge computational overhead in each pipeline stage.…”

Section: Related Workmentioning

confidence: 99%

“…To show the superiority of the proposed design, we have also compared it with other related 2D convolvers. As shown in Table 1, the pixel access rate, and resource utilization of the convolvers proposed in [5], [6], and [19] are compared with approximate and combined convolvers. In this discussion, the FPGA devices are altered to make a fair comparison with other designs.…”

Section: Resource Utilizationmentioning

confidence: 99%

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Real-time approximate and combined 2D convolvers for FPGA-based image processing

et al. 2023

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Convolution widely has been used as the main part of the improvement in digital image processing applications. In convolutional computations, a large number of memory accesses and a huge amount of computations challenge its performance. Many of the related proposed convolvers are based on exact computations. Although exact convolvers keep the accuracy of the convolution operation at the top level, sometimes by missing a negligible amount of accuracy, the performance can be improved. Approximate computing is a new technique for solving computation overhead problems. In this paper, approximate 2D convolvers are presented which minimize the memory access rate and computations by a special factor of Multiply-and-Accumulate (MAC) terms. On the other hand, to preserve the flexibility for supporting different required accuracy, the proposed approximate convolvers are combined with the exact designs with real-time pre-processing stages by exploiting innovative methods which manage the hardware overhead. In comparison to conventional convolvers, the proposed designs improve the number of active resources which causes a significant reduction in power consumption. For 3 × 3 kernel size, the evaluation results on the Xilinx Virtex-7 (XC7V2000t) FPGA device show 34% and 20% power optimization of the proposed approximate and combined convolvers respectively, in comparison to Exact Convolver (EC). Also, this improvement grows by increasing the kernel size. Finally, a comparison based on RMSE and PSNR for different sample images and filters reveals that the error rate and image quality reduction are acceptable for many real-time image processing applications.

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Section: Related Workmentioning

confidence: 99%

Section: Resource Utilizationmentioning

confidence: 99%

Real-time approximate and combined 2D convolvers for FPGA-based image processing

et al. 2023

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“…The work in [18] presents a multiplierless, coefficient independent filter that also utilizes a mechanism for zero padding at the borders. They also compare against a baseline architecture that uses embedded multipliers and other work in the literature, with the most relevant to this article being [31]- [33]. Bailey and Ambikumar [10] explored border handling in transposed form filters.…”

Section: F Comparisons With Previous Workmentioning

confidence: 99%

High Throughput Spatial Convolution Filters on FPGAs

Ioannou

Al-Dujaili

Fahmy

2020

IEEE Trans. VLSI Syst.

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“…The ICAP with a 32-bit, 100 MHz streaming interface provides up to 400 MB/s reconfiguration throughput. However, a number of alternative reconfiguration controllers [24,16,25] have been implemented in order to speed up the reconfiguration process.…”

Section: Run-time Partial Reconfigurable Computing Technologymentioning

confidence: 99%

An adaptive high-throughput edge detection filtering system using dynamic partial reconfiguration

Orlandić

Svarstad

2018

J Real-Time Image Proc

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This paper proposes an architecture consisting of various edge detection filters implemented on modern FPGA platforms exploiting a feature of Dynamic Partial Reconfiguration (DPR). The developed system targets small scale systems, and its use in the educational setting can be of great interest. Two dimensional convolution is the most common operation in digital video/image processing and its implementation is highly demanding in terms of computational intensity, high-throughput and hardware resources. In the case of a variety of filtering techniques used for edge detection, the hardware resources become a constraint, in particular when using convolution kernels with varying parameters and sizes. DPR introduces significant functional density and increased flexibility by providing logic switching within a constrained hardware area. Furthermore, parallel and pipelined hardware solutions for filter implementation overcome computational performance of software solutions and increase effectiveness compared to static hardware solution. The advantages of accommodating a number of various algorithms within the same datapath at low cost and considerable time is exploited in the proposed work. The effectiveness of the DPR feature for edge detection application is tested on the filter scenarios varying in sizes, complexity and intensity of computation, where the resource

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Run-time self-reconfigurable 2D convolver for adaptive image processing

Cited by 19 publications

References 5 publications

Real-time approximate and combined 2D convolvers for FPGA-based image processing

Real-time approximate and combined 2D convolvers for FPGA-based image processing

High Throughput Spatial Convolution Filters on FPGAs

An adaptive high-throughput edge detection filtering system using dynamic partial reconfiguration

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