RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators

Vacca, Eleonora; Ajmone, Giorgio; Sterpone, Luca

doi:10.1109/iccd58817.2023.00095

Cited by 3 publications

References 23 publications

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A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators

Filippas,

Peltekis,

Titopoulos

et al. 2024

IEEE Access

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Convolution neural networks (CNNs) are widely applied in many machine learning applications. Hardware acceleration for CNNs is crucial, given their high computational intensity and the demand for enhanced energy efficiency and reduced latency in application response. This work leverages the simplicity of modelling CNN structure in Python with the flexibility of High-Level synthesis to automate the creation of CNN dataflow hardware accelerators. The methodology emphasizes ease of design, enabling users to effortlessly generate hardware accelerators directly from the corresponding Tensorflow or PyTorch CNN models. The proposed generator incorporates multiple optimization knobs, facilitating the automatic exploration of diverse architectural alternatives to enhance performance and improve energy efficiency. Besides well-known optimization knobs, this work integrates for the first time functional safety features and optimized buffering architectures. It also introduces various design options related to data representation and arithmetic. Experimental results highlight (a) the effectiveness of the proposed approach in automatically synthesizing optimized CNN dataflow accelerators and (b) the improved characteristics offered by the introduced generator compared to state-of-the-art approaches.

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