Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals

Dimić, Vladimir; Moretó, Miquel; Casas, Marc; Valero, Mateo

doi:10.1007/978-3-319-64203-1_18

Cited by 7 publications

(7 citation statements)

References 23 publications

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“…The runtime system can transparently manage GPUs [7], [76], FPGA accelerators [18], [85], multi-node clusters [20], [27], [28], heterogeneous memories [4], [63], scratchpad memories [5], NUMA [81], [82] and cache coherent NUMA [21], [23] systems. Adding hardware support, the runtime system can guide cache replacement [37], [65], cache coherence deactivation [22], cache prefetching [47], [75], cache communication mechanisms in producer-consumer task relationships [64], [66], reliability and resilience [51]- [53], value approximation [19], and DVFS to accelerate critical tasks [26].…”

Section: Task Dataflow Programming Modelsmentioning

confidence: 99%

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models

Caheny

Alvarez

Casas

et al. 2022

SC22: International Conference for High Performance Computing, Networking, Storage and Analysis

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In high performance processors, the design of onchip memory hierarchies is crucial for performance and energy efficiency. Current processors rely on large shared Non-Uniform Cache Architectures (NUCA) to improve performance and reduce data movement. Multiple solutions exploit information available at the microarchitecture level or in the operating system to optimize NUCA performance. However, existing methods have not taken advantage of the information captured by task dataflow programming models to guide the management of NUCA caches.In this paper we propose TD-NUCA, a hardware/software codesigned approach that leverages information present in the runtime system of task dataflow programming models to efficiently manage NUCA caches. TD-NUCA identifies the data access and reuse patterns of parallel applications in the runtime system and guides the operation of the NUCA caches in the hardware. As a result, TD-NUCA achieves a 1.18x average speedup over the baseline S-NUCA while requiring only 0.62x the data movement.

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Section: Task Dataflow Programming Modelsmentioning

confidence: 99%

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models

Caheny

Alvarez

Casas

et al. 2022

SC22: International Conference for High Performance Computing, Networking, Storage and Analysis

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“…Recent works (Dimić et al 2017;Manivannan et al 2016;Pan and Pai 2015) leverage information about tasks and its working set in task-based programming models to improve efficiency of the shared LLC. However, like other local schemes, they only address cache inefficiency at a single level of the cache hierarchy.…”

Section: Related Workmentioning

confidence: 99%

Global Dead-Block Management for Task-Parallel Programs

Manivannan

Pericàs

Papaefstathiou

et al. 2018

ACM Trans. Archit. Code Optim.

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Task-parallel programs inefficiently utilize the cache hierarchy due to the presence of dead blocks in caches. Dead blocks may occupy cache space in multiple cache levels for a long time without providing any utility until they are finally evicted. Existing dead-block prediction schemes take decisions locally for each cache level and do not efficiently manage the entire cache hierarchy. This article introduces runtime-orchestrated global dead-block management, in which static and dynamic information about tasks available to the runtime system is used to effectively detect and manage dead blocks across the cache hierarchy. In the proposed global management schemes, static information (e.g., when tasks start/finish, and what data regions tasks produce/consume) is combined with dynamic information to detect when/where blocks become dead. When memory regions are deemed dead at some cache level(s), all the associated cache blocks are evicted from the corresponding level(s). We extend the cache controllers at both private and shared cache levels to use the aforementioned information to evict dead blocks. The article does an extensive evaluation of both inclusive and non-inclusive cache hierarchies and shows that the proposed global schemes outperform existing local dead-block management schemes.

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“…Thus, the runtime system contains by design the information about the parallel code and the underlying hardware, and therefore can serve as an interface between these two layers. The usefulness of runtime system-level information in the context of HPC applications and hardware has been extensively studied [1,4,5,7,10,11,19,24,38].…”

Section: Introductionmentioning

confidence: 99%

PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy

Dimić

Moretó

Casas

et al. 2021

Euro-Par 2021: Parallel Processing

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The ever-increasing gap between the processor and main memory speeds requires careful utilization of the limited memory link. This is additionally emphasized for the case of memory-bound applications. Prioritization of memory requests in the memory controller is one of the approaches to improve performance of such codes. However, current designs do not consider high-level information about parallel applications. In this paper, we propose a holistic approach to this problem, where the runtime system-level knowledge is made available in hardware. Processor exploits this information to better prioritize memory requests, while introducing negligible hardware cost. Our design is based on the notion of critical path in the execution of a parallel code. The critical tasks are accelerated by prioritizing their memory requests within the on-chip memory hierarchy. As a result, we reduce the critical path and improve the overall performance up to 1.19× compared to the baseline systems.

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Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals

Cited by 7 publications

References 23 publications

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models

Global Dead-Block Management for Task-Parallel Programs

PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy

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