S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

Kim, J.V.; Oh, Hansu; Woo, D. S.; Lee, Y.S.; Kim, D.H.; Kim, S.E.; Ha, Geun-Hyoung; Kim, H.J.; Kang, Nam-Soo; Park, J.M.; Hwang, Young‐Ha; Kim, D.I.; Park, B.J.; Huh, Myung Soo; Lee, B.H.; Kim, S.B.; Cho, M.H.; Jung, Myoung-Ho; Kim, Y.I.; Jin, Chun Yan; Shin, Dongsuk; Shim, M.S.; Lee, C.S.; Lee, W.S.; Park, J.C.; Jin, Gyoyoung; Park, Y.J.; Kim, Kinam

doi:10.1109/.2005.1469201

Cited by 35 publications

(24 citation statements)

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“…This type of transistor has large gate-drain overlap region and GIDL current is the most important component of the leakage current. [18][19][20][21][22] 1k cell array test element group's (TEG) in which about 1000 cell transistors are connected in parallel were used to measure GIDL-RTS as shown in Fig. 2.…”

Section: Experimental Methodsmentioning

confidence: 99%

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

Kim

Kim³

et al. 2010

Jpn. J. Appl. Phys.

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We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxidesemiconductor field-effect transistors (MOSFETs). #

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Section: Experimental Methodsmentioning

confidence: 99%

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

Kim

Kim³

et al. 2010

Jpn. J. Appl. Phys.

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“…With decreasing dynamic random-access memory (DRAM) cell size, a recessed channel array transistor (RCAT) has been proposed to overcome the short channel effect (SCE) of conventional MOSFETs with planar channels. Although the recessed channel of RCAT has improved short channel effect (SCE), RCAT suffers from low driving current and V TH sensitivity due to the shape of the bottom corner of the recessed channel [1]. To solve these problems, a saddle FinFET (S-FinFET) has been proposed with a tri-gate that wraps both the recessed channel surface and the side surface [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

et al. 2018

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In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower I off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I off characteristics as gate channel length decreased.Keywords: gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (I on ); off-current (I off ); subthreshold slope (SS); threshold voltage (V TH ); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); technique for the buried insulator under the cell transistor [7,8]. We analyzed electrical characteristics of this proposed device and compared them with those of conventional S-FinFETs of the same size. We also showed the optimized parameters of the buried insulator using a three-dimensional (3D) device simulator in sub-30 nm cell size [9]. The device described in this paper has reliable source/drain (S/D) doping concentration with a Gaussian profile. The simulator is well tuned to predict DRAM cell transistor leakage distribution [10,11]. Device StructureThe partial isolation type S-FinFET (Pi-FinFET) is a structure with a buried insulator at a certain depth from the storage node of a conventional S-FinFET. Figure 1a shows a 3D schematic of a Pi-FinFET. Silicon film thickness, buried insulator thickness, and L in , as shown in Figure 1a,b, are defined as the distance from the contact surface of the storage node to the buried insulator, the thickness of the buried insulator in the direction perpendicular to the channel, and the distance from the side gate oxide to the buried insulator, respectively. L g , L side , L ov_xj , and L ov_side represent gate channel length, the length of the side-gate in the direction parallel to the channel, the overlapped length of the side-gate and S/D doping region shown in Figure 1a, and the side-channel width shown in Figure 1c, respectively. When L side and L ov_xj are increased, the width of the overlap region of the gate and the S/D region will also increase. The n + poly gate with a gate work function of 4.2 eV was applied. L g , L side , L ov_side and the recessed depth are 30 nm, 42 nm, 10 nm, and 100 nm, respectively. RFinFET is the modified S-FinFET with a structure in which the overlap region between the side-gate and the S/D region is removed [5]. Therefore, the Pi-FinFETs proposed in this paper can be divided into Pi-SFinFET and Pi-RFinFET depending on the presence or absence of the overlap region between the side-gate and the S/D region. Namely, in...

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“…Researchers have proposed several different devices for a bitcell transistor to reduce leakages [21][22][23][24][25][26][27][28]. Samsung proposed the recessed channel array transistor (RCAT) with 88 nm DRAM technology [21] and scaling RCAT down to 50 nm process [22].…”

Section: Transistor Model and Scalingmentioning

confidence: 99%

“…Samsung also proposed a sphere-shaped recessed channel array transistor (SRCAT) with the 70 nm process and expected extendable scaling down to sub-50 nm process. SRCAT provides more recessed channel effect than RCAT [23]. FinFET or its hybrid are also studied as a bitcell transistor in DRAMs [25][26][27]30].…”

Section: Transistor Model and Scalingmentioning

confidence: 99%

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

Park

Davis

Franzon

2019

IEEE Trans. Circuits Syst. I

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Three-dimensional stacked DRAM technology has emerged recently. Many studies have shown that 3D DRAM is most promising solutions for future memory architecture to fulfill high bandwidth and high-speed operation with low energy consumption. It is necessary to explore 3D DRAM design space and find the optimum DRAM architecture in different system needs. However, a few studies have offered models for power and access latency calculations of DRAM designs in limited ranges. This has led to a growing gap in knowledge of the area, timing, and energy modeling of 3D DRAMs for utilization in the design process of processor architectures that could benefit from 3D DRAMs. This paper presents a circuit level DRAM Area, Timing, and Energy model (DATE) which supports 3D DRAM design with TSV. DATE provides front-end and back-end DRAM process roadmap from 90 nm to 16 nm node and provides a broader range 3D DRAM design model along with emerging transistor device. DATE is successfully validated against several commodity planar and 3D DRAMs and published prototype DRAMs with emerging device. Energy verification has a mean error of about -5% to 1%, with a standard deviation of up to 9.8%. Speed verification has a mean error of about -13% to -27% and a standard deviation of up to 24%. In the case of the area, the bank has a mean error of -3% and the whole die has a mean error of -1%. The standard deviation for area is up to 4.2%. In the case study, we demonstrate that 1Gb DDR3 DRAM designs achieve up to about 0.7 Gb/sec data throughput and energy efficiency of 510 bit/nJ using 3D design options with 16 nm DRAM technology.

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S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

Cited by 35 publications

References 0 publications

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

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