Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations

Abstract

Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. This presentation brings in the idea of "safe operation region" to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding timeconsuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process.

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

“…While the effects of such issues on performance figures like leakage power and delay modeling have been profoundly inquired [1][2] [16] [18], their influence on the reliability of digital designs over the years is being modelled and quantified [4][11] [13] [12] and there is a general correspondence that reliability be a key topic of future digital integrated circuits [14].…”

Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops

“…nvasive uninterrupted scaling of CMOS and FinFET technologies to nano-scale level leads to various fallouts such as variability of process parameters and aging due to Negative Bias Temperature Instability (NBTI). While the effects of such issues on performance figures like leakage power and delay modeling have been profoundly inquired [1][2] [16] [18], their influence on the reliability of digital designs over the years is being modelled and quantified [4] [11][13] [12] and there is a general correspondence that reliability be a key topic of future digital integrated circuits [14].…”