SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware

Beaumont, Olivier; Hopkins, David; Newby, J.

doi:10.1109/date.2012.6176642

Cited by 34 publications

(27 citation statements)

References 14 publications

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“…With more than two IP cores, a voting protocol can determine which output to select in case of disagreement. Beaumont et al [2] pioneered this approach, along with fragmented execution to limit access to code and data. We use a similar scheme as the prior work, except we limit replication to the outer-most cryptographic modules used in onion-encryption, which we suggest is sufficient for ensuring confidentiality.…”

Section: R Replicationmentioning

confidence: 99%

“…Waksman and Sethumadhavan [4] use cryptography at the granularity of functional units in a processor to defend against value-triggered Trojans, but only against the untrusted designer. Replication using functionally-equivalent variants was first proposed by McIntyre et al [5] at the software-level to detect hardware Trojans, and Beaumont et al [2] propose an architectural solution using replication, voting, and fragmented execution. These works focus on untrusted design, and attacks from untrusted foundry or end-user void security guarantees.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets

Bloom

Narahari

Simha

et al. 2015

2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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Hardware Trojans compromise security by invalidating the assumption that hardware provides a root-of-trust for secure systems. We propose a novel approach for an FPGA system-on-chip (SoC) to ensure confidentiality of trusted software despite hardware Trojan attacks. Our approach employs defensive techniques that feature morphing on-chip resources for moving target defense against fabrication-time Trojans, onionencryption for confidentiality, and replication of functionallyequivalent variants of processing elements with arbitrated voting for resilience to design-time Trojans. These techniques are enabled by partial runtime reconfiguration (PRR) and are managed by a hardware abstraction layer (HAL) that reduces developer burden. We call our approach the Morph Onion-encryption Replication PRR HAL, or MORPH. MORPH aims to provide a stable interface for embedded systems developers to use in deploying applications that are resilient to hardware Trojans.

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Section: R Replicationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets

Bloom

Narahari

Simha

et al. 2015

2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

View full text Add to dashboard Cite

show abstract

“…In [14], a trojan detection and prevention scheme is proposed for homogeneous systems. Each program is partitioned into segments and redundantly executed on three or more cores, aiming at limiting the data access capability of each core.…”

Section: Related Workmentioning

confidence: 99%

Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling

Liu

Rajendran

Yang

et al. 2013

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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Outsourcing of the various aspects of IC design and fabri cation flow strongl y questions the classic assumption that "hardware is trustworth y ". Multiprocessor S y stem-on-Chip (MPSoC) platforms face some of the most demanding securit y concerns, as they process, store, and communicate sensitive information using third-part y intellectual property (3PIP) cores that ma y be untrustworth y . The complexit y of an MPSoC makes it expensive and time consuming to full y anal y ze and test it during the design stage. Consequently, the trustworthiness of the 3PIP components cannot be ensured. To protect MPSoCs against malicious modifications, we propose to incorporate trojan toleration into MPSoC platforms b y revising the task scheduling step of the MPSoC design process. We impose a set of securit y -driven diversit y constraints into the scheduling process, enabling the s y stem to detect the presence of malicious modifications or to mute their effects during application execution. Furthermore, we pose the securit y -constrained MPSoC task scheduling as a multi-dimensional optimization problem, and propose a set of heuristics to ensure that the introduced securit y constraints can be fulfilled with minimum performance and hardware overhead.

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“…In this paper, we propose a securitydriven MPSoC task scheduling technique to account for the untrustworthiness of the 3PIP cores. Comparing to existing trojan detection and prevention techniques [6], [7], [8], our main contribution is the incorporation of diversity into MPSoC task schedules. As multiple copies of the same 3PIP may be instantiated in the target MPSoC, diversity is essential to reduce false negatives: on one hand it prevents two copies of a task from producing the same incorrect outputs, and on the other hand it isolates potential trojans, preventing them from sending triggering messages through undesired communication paths.…”

Section: Introductionmentioning

confidence: 99%

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling

Liu

Rajendran

Yang

et al. 2014

IEEE Trans. Emerg. Topics Comput.

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Multiprocessor System-on-Chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The trend of outsourcing design and fabrication strongly questions the assumption that 3PIP components are trustworthy. However, the complexity of an MPSoC makes it expensive and time consuming to fully analyze and test it during the design stage.To protect MPSoCs against malicious modifications, we propose to incorporate trojan toleration into MPSoC platforms by revising the task scheduling step of the MPSoC design process. We impose a set of securitydriven diversity constraints into the scheduling process, enabling the system to detect the presence of malicious modifications or to mute their effects during application execution. Furthermore, we pose the securityconstrained MPSoC task scheduling as a multi-dimensional optimization problem, and propose a set of heuristics to ensure that the introduced security constraints can be fulfilled within minimum impact on the other design goals such as performance and hardware. Experimental results show that without any extra cores, security constraints can be fulfilled within 4 vendors and 81% overhead in schedule length. We believe that this extra cost is acceptable for building a trustworthy MPSoCs for critical infrastructures.

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SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware

Cited by 34 publications

References 14 publications

FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets

FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets

Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling

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