Safety, Security and Multicore

Parkinson, Paul

doi:10.1007/978-0-85729-133-2_13

Cited by 15 publications

(6 citation statements)

References 3 publications

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“…In the domain of high-assurance systems, an increasing trend is the adoption of multicore processor to fulfil demands of higher computing power [Parkinson 2011]. The overall performance of systems is improved by concurrent execution of instructions in multicore processors.…”

Section: Dealing With Multicore and Concurrencymentioning

confidence: 99%

High-Assurance Separation Kernels: A Survey on Formal Methods

Zhao¹,

Sanán²,

Zhang³

et al. 2017

Preprint

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Separation kernels provide temporal/spatial separation and controlled information flow to their hosted applications. They are introduced to decouple the analysis of applications in partitions from the analysis of the kernel itself. More than 20 implementations of separation kernels have been developed and widely applied in critical domains, e.g., avionics/aerospace, military/defense, and medical devices. Formal methods are mandated by the security/safety certification of separation kernels and have been carried out since this concept emerged. However, this field lacks a survey to systematically study, compare, and analyze related work. On the other hand, high-assurance separation kernels by formal methods still face big challenges. In this paper, an analytical framework is first proposed to clarify the functionalities, implementations, properties and standards, and formal methods application of separation kernels. Based on the proposed analytical framework, a taxonomy is designed according to formal methods application, functionalities, and properties of separation kernels. Research works in the literature are then categorized and overviewed by the taxonomy. In accordance with the analytical framework, a comprehensive analysis and discussion of related work are presented. Finally, four challenges and their possible technical directions for future research are identified, e.g. specification bottleneck, multicore and concurrency, and automation of full formal verification.CCS Concepts: •Software and its engineering → Operating systems; Formal methods; •Computer systems organization → Real-time operating systems; •Security and privacy → Formal methods and theory of security;

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Section: Dealing With Multicore and Concurrencymentioning

confidence: 99%

High-Assurance Separation Kernels: A Survey on Formal Methods

Zhao¹,

Sanán²,

Zhang³

et al. 2017

Preprint

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“…Transferring data through a shared memory region is strictly prohibited because of a potential vulnerability [25]. As shown in Figure 2, the I/O proxy first retrieves sensor data from the plant and then transfers it to the two controllers.…”

Section: B Design Considerationsmentioning

confidence: 99%

“…Also, we chose to use an SPM instead of shared memory (through a cache) as the buffer for the traces because an SPM has a lower access latency. The shared memory communication can also open up potential security breaches [25].…”

Section: Timing Trace Module (Ttm)mentioning

confidence: 99%

“…1 A safety-critical or life-critical system is one where failure or malfunction may result in death or serious injury to humans, loss or severe damage to equipment and/or the environment. the multiple cores and could result in security vulnerabilities [25]. For example, malicious entities could snoop on privileged information used/generated by critical code running on alternate cores, high-priority tasks could be prevented from executing by a denial-of-service attack on the shared resources (e.g., keeping the bus occupied by large DMA transfers could prevent the high priority task from obtaining the memory reads it requested), etc.…”

Section: Introductionmentioning

confidence: 99%

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SecureCore: A multicore-based intrusion detection architecture for real-time embedded systems

Yoon

Mohan

Choi

et al. 2013

2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Security violations are becoming more common in real-time systems -an area that was considered to be invulnerable in the past -as evidenced by the recent W32.Stuxnet and Duqu worms. A failure to protect such systems from malicious entities could result in significant harm to both humans as well as the environment. The increasing use of multicore architectures in such systems exacerbates the problem since shared resources on these processors increase the risk of being compromised. In this paper, we present the SecureCore framework that, coupled with novel monitoring techniques, is able to improve the security of realtime embedded systems. We aim to detect malicious activities by analyzing and observing the inherent properties of the real-time system using statistical analyses of their execution profiles. With careful analysis based on these profiles, we are able to detect malicious code execution as soon as it happens and also ensure that the physical system remains safe.

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“…A compounding issue that must be addressed when moving to modern architecture frameworks are safety and security requirements [1]. Parkinson defines, in [2], safety as where the system must not harm the world and security as where the world must not harm the system. These requirements constrict the program's ability to select any commercial operating system.…”

Section: Introductionmentioning

confidence: 99%

An Evolutionary Approach for the Hierarchical Scheduling of Safety- and Security-Critical Multicore Architectures

2020

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The aerospace and defense industry is facing an end-of-life production issue with legacy embedded uniprocessor systems. Most, if not all, embedded processor manufacturers have already moved towards system-on-a-chip multicore architectures. Current scheduling arrangements do not consider schedules related to safety and security. The methods are also inefficient because they arbitrarily assign larger-than-necessary windows of execution. This research creates a hierarchical scheduling framework as a model for real-time multicore systems to integrate the scheduling for safe and secure systems. This provides a more efficient approach which automates the migration of embedded systems’ real-time software tasks to multicore architectures. A novel genetic algorithm with a unique objective function and encoding scheme was created and compared to classical bin-packing algorithms. The simulation results show the genetic algorithm had 1.8–2.5 times less error (a 56–71% difference), outperforming its counterparts in uniformity in utilization. This research provides an efficient, automated method for commercial, private and defense industries to use a genetic algorithm to create a feasible two-level hierarchical schedule for real-time embedded multicore systems that address safety and security constraints.

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Safety, Security and Multicore

Cited by 15 publications

References 3 publications

High-Assurance Separation Kernels: A Survey on Formal Methods

High-Assurance Separation Kernels: A Survey on Formal Methods

SecureCore: A multicore-based intrusion detection architecture for real-time embedded systems

An Evolutionary Approach for the Hierarchical Scheduling of Safety- and Security-Critical Multicore Architectures

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