SAGE: an automatic analyzing system for a new high-performance SoC architecture––processor-in-memory

Abstract

Abstract. Continuous improvements in semiconductor fabrication density are supporting new classes of System-on-a-Chip (SoC) architectures that combine extensive processing logic/processor with high-density me mory. Such architectures are generally called Processor-in-Memory or Intelligent Memory and can support high-performance computing by reducing the performance gap between the processor and the memory. This architecture combines various processors in a single system. These processors are characterized by their computation and memory-access capabilities. Therefore, a novel strategy must be developed to identify their capabilities and dispatch the most appropriate jobs to them in order to exploit them fully. Accordingly, this study presents an automatic source-to-source parallelizing system, called SAGE, to exploit the advantages of Processor-in-Memory architectures. Unlike conventional iteration-based parallelizing systems, SAGE adopts statement-based analyzing approaches. This study a ddresses the one-host and one-memory processor configuration. The strategy of the SAGE system, in which the original program is decomposed into blocks and a feasible execution schedule is produced for the host and memory processors, is investigated as well. The experimental results for real benchmarks are also discussed.

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

“…These generators can be optimized by applying bus power consumption minimizing techniques. For example, the activity on memory address buses can be reduced by analyzing access patterns and organizing the arrays in memory by the following: • looking at data transfers on buses in order to limit line commutation [22]; • accessing adjacent data in memory to limit the commutations on address buses [23], [24]. Various bus encoding schemes [25]- [29] have been proposed to decrease the number of transitions.…”