SALSA: a new approach to scheduling with timing constraints

Nestor, John A.; Krishnamoorthy, Ganesh

doi:10.1109/43.238604

Cited by 57 publications

(3 citation statements)

References 22 publications

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“…SALSA, a scheduling method in HLS for optimizing HW resource cost under the latency constraint, was proposed in Nestor and Krishnamoorthy. 15 It employs an SA-based approach for improving the initial schedule that satisfies the timing constraint by exploring alternative schedules to minimize resource cost. Again, the energy and reliability considerations were left out of the HLS process.…”

Section: Related Workmentioning

confidence: 99%

“…Statistical analysis is important if we wish to adopt the optimal cooling strategy for the problem at hand. 63 The cooling schedule adopted in this study is a frequently used cooling approach known as the geometric schedule that originates from Kirkpatrick et al 43 It is formulated in Equation (15), where α c is usually chosen to be a positive constant smaller than but close to 1 (0:8 ≥ α c ≤ 0:99).…”

Section: Annealing Schedulementioning

confidence: 99%

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Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Dilek,

Tosun,

Cakin

2023

Circuit Theory & Apps

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SummaryIntegrated circuits have become more vulnerable to soft errors due to smaller transistor sizes and lower threshold voltage levels. Energy reduction methods make circuits more error‐prone since even the smallest amounts of environmental radiation can cause a bit flip. Furthermore, redundancy‐based error detection and correction methods induce higher costs and area overhead. Thus, several conflicting parameters may need to be considered during embedded system design (e.g., area, performance, energy, and reliability). High‐level synthesis (HLS) is the most practical design step to consider all these parameters as complexity increases at lower levels. HLS can be viewed as a multi‐objective optimization problem of finding a set of Pareto‐optimal designs, allowing designers to choose the ones that best fit the requirements. Moreover, the number of synthesis options superlinearly affects the search space growth, necessitating efficient optimization methods. In this study, we propose simulated annealing (SA)‐based HLS methods for multi‐Vcc application‐specific integrated circuit design, aiming to optimize energy consumption and reliability under the area and latency constraints. Furthermore, we use duplication to improve design reliability as much as the constraints allow. We compared our methods against genetic algorithm (GA)‐based and integer linear programming (ILP)‐based methods and showed their effectiveness in finding optimum or near‐optimum results in a short running time. SA‐based methods achieved up to 21.20% reliability improvement on average and up to 38% energy reduction on average, while preserving the reliability value against the GA‐based metaheuristic counterpart under joint reliability and energy optimization on four HLS benchmarks.

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Section: Related Workmentioning

confidence: 99%

Section: Annealing Schedulementioning

confidence: 99%

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

Dilek,

Tosun,

Cakin

2023

Circuit Theory & Apps

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“…We obtain empirical correlation results for the MR-LCS HLS problem for 11 DFGs in [9] by varying the degree of FU-centric optimization in the initial scheduling stage via using the following different well-known algorithms ranging from the seminal/classical and low-to medium quality (LS, FDS, SA) to the state-of-the-art approximate and high quality (FALLS) to an optimal formulation with exponential complexity (ILP): list scheduling (LS) [5], force-directed scheduling (FDS) [7], a simulated-annealing-based technique (SA) [8], FALLS [3], and ILP [6]. We note that for keeping the complexity of our empirical and probabilistic analysis tractable, we do not perform module selection (e.g., [4]) here, but believe that the conclusions we derive should hold when module selection is performed.…”

Section: Scheduling Techniques For Obtaining Varying Degrees Of Fu Op...mentioning

confidence: 99%

On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis

Dutt

Zhang

Shi

2021

2021 22nd International Symposium on Quality Electronic Design (ISQED)

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As the technology node of VLSI designs advances to sub-10 nm, two interconnect-centric metrics of a circuit, the interconnect complexity (either number of interconnects or wirelength/WL) and congestion, become critically important across all design stages alongside conventional resource or function-unit (FU)-centric metrics like area/number-of-FUs and leakage power. High Level synthesis (HLS), one of the earliest and most impactful design stages, rarely monitors interconnect metrics, which makes their recovery at later stages very difficult. HLS algorithms and tools typically perform FU-centric minimization via operation scheduling, module selection (S&MS) and binding. As a consequence, it mostly overlooks interconnect-based metrics. In this paper, we explore whether this can adversely affect interconnect metrics, and in general explore the correlation between FUcentric optimization in S&MS, and the resulting interconnect metrics co-optimized (along with FU metrics) in the later binding stage(s). For this purpose we develop a probabilistic analysis for post-scheduling binding to estimate interconnect metrics, and verify its accuracy by comparison to empirical results across different scheduling techniques that generate different degrees of FU optimization. Based on both empirical and analytical results we predict how interconnects metrics will pan out with different degrees of FU optimization. Finally, based on our analysis, we also provide suggestions to improve interconnect metrics for whatever FU optimization degree an available S&MS technique can achieve.

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